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Chapter 14

Chapter 14. Arithmetic Circuits. Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003. A Generic Digital Processor. Building Blocks for Digital Architectures. Arithmetic and Unit. Bit-sliced datapath. ( adder, multiplier, shifter, comparator, etc.). -. Memory. - RAM, ROM, Buffers, Shift registers.

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Chapter 14

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  1. Chapter 14 Arithmetic Circuits Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003

  2. A Generic Digital Processor

  3. Building Blocks for Digital Architectures Arithmetic and Unit Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) - Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus

  4. Intel Microprocessor Itanium has 6 integer execution units like this

  5. Bit-Sliced Design

  6. Itanium Integer Datapath Fetzer, Orton, ISSCC’02

  7. Adders

  8. Full-Adder (FA) Generate (G) = AB Propagate (P) = A B Å Delete = A B

  9. Boolean Function of Binary Full-Adder CMOS Implementation

  10. Express Sum and Carry as a function of P, G, D Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Å Delete = A B S C D and P Can also derive expressions for and based on o Note that we will be sometimes using an alternate definition for + Propagate (P) = A B

  11. A B A B A B A B 0 0 1 1 2 2 3 3 C C C C C i ,0 o ,0 o ,1 o ,2 o ,3 FA FA FA FA = ( C ) i ,1 S S S S 0 1 2 3 Ripple-Carry Adder Critical Path Worst-case delayis linear with the number of bits tadder = (N-1)tcarry + tsum td = O(N) • Propagation delay (or critical path) is the worst-case delay over all possible input patterns • A= 0001, B=1111, trigger the worst-case delay • A: 0  1, and B= 1111 fixed to set up the worst-case delay transition.

  12. Complimentary Static CMOS Full Adder 28 Transistors • Logic effort of Ci is reduced to 2 (c.f., A and B signals) • Ci is late arrival signal  near the output signal • Co needs to be inverted  Slow down the ripple propagate

  13. Inversion Property

  14. Minimize Critical Path by Reducing Inverting Stages • Exploit Inversion Property • Reduce One inverter delay in each Full-adder (FA) unit

  15. A Better Structure: The Mirror Adder Exploring the “Self-Duality” of the Sum and Carry functions

  16. Mirror Adder: Stick Diagram

  17. Mirror Adder Design • The NMOS and PMOS chains are completely symmetrical • A maximum of two series transistors can be observed in the carry-generation circuitry  for good speed. • When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. • The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . • The transistors connected to Ci are placed closest to the output.

  18. Transmission-Gate Full Adder (24T) • Same delay for Sum and Carry  Multiplier design

  19. Manchester Carry-Chain Adder Static Circuits Dynamic Circuits

  20. Manchester Carry Chain

  21. Manchester Carry-Chain Adder

  22. Carry-Bypass Adder Also called Carry-Skip

  23. Carry-Bypass Adder (cont.) tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum M bits form a Section  (N/M) Bypass Stages

  24. Carry Ripple versus Carry Bypass Wordlength (N) > 4~8 is better for Bypass Adder

  25. Carry-Select Adder

  26. Carry Select Adder: Critical Path

  27. Linear Carry Select

  28. Square Root Carry Select N-bit adder with P stages, 1st stage adds M bits 

  29. Adder Delays - Comparison

  30. Look-ahead Adder - Basic Idea

  31. Look-Ahead: Topology Expanding Lookahead equations: All the way:

  32. Multipliers

  33. Binary Multiplication

  34. Binary Multiplication

  35. Array Multiplier

  36. MxN Array Multiplier — Critical Path Critical Path 1 & 2

  37. Carry-Save Multiplier

  38. Multiplier Floorplan

  39. Wallace-Tree Multiplier

  40. Wallace-Tree Multiplier

  41. Wallace-Tree Multiplier

  42. Multipliers —Summary • Identify Critical Paths • Other Possible techniques: • Data Encoding (Booth) • Logarithmic v.s. Linear (Wallace Tree Multiplier) • Pipelining

  43. Shifters

  44. The Binary Shifter

  45. The Barrel Shifter Area Dominated by Wiring

  46. 4x4 barrel shifter Widthbarrel ~ 2 pm M

  47. Logarithmic Shifter

  48. 0-7 bit Logarithmic Shifter A 3 Out3 A 2 Out2 A 1 Out1 A 0 Out0

  49. Summary • Datapath designs are fundamentals for high-speed DSP, Multimedia, Communication digital VLSI designs. • Most adders, multipliers, division circuits are now available in Synopsys Designware under different area/speed constraint. • For details, check “Advanced VLSI” notes, or “Computer Arithmetic” textbooks

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