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Understanding the NICEWAY Exercise in Microelectronics: A Hands-On Laboratory Approach

The NICEWAY Exercise is an essential component of the Microelectronics course, guiding students through process and device simulation, IC fabrication processes, and the significance of simulations. This practical experience involves three lab sessions, focusing on aspects such as oxidation, implantation, and doping densities. Students will learn about input and output characteristics of devices, including breakdown and threshold voltages. Proper preparation is crucial, and students must complete required readings and bring necessary materials to each session, ensuring a comprehensive understanding of semiconductor fabrication techniques.

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Understanding the NICEWAY Exercise in Microelectronics: A Hands-On Laboratory Approach

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  1. The NICEWAY EXERCISE Dr. Peter EwenProf. Rebecca Cheung This is taken only by students doing MICROELECTRONICS 3

  2. THE NICEWAY EXERCISE • PROCESS AND DEVICE SIMULATORS • IC FABRICATION PROCESSES • IMPORTANCE OF SIMULATIONS • THE NICEWAY EXERCISE

  3. e.g. oxidation time, oxidation temperature, implant dose & energy INPUT PROCESS SIMULATOR DEVICE STRUCTURE DOPING DENSITIES ND gate field oxide concentration OUTPUT NA source drain depth

  4. device structure, doping densities INPUT DEVICE SIMULATOR ELECTRICAL PROPERTIES IO • OUTPUT CHARACTERISTICS • BREAKDOWN VOLTAGE • THRESHOLD VOLTAGE • etc. OUTPUT VO

  5. FABRICATION DETAILS PROCESS SIMULATOR device structure doping densities DEVICE SIMULATOR ELECTRICAL PROPERTIES

  6. THE 4 MAIN IC FABRICATION PROCESSES SiO2 oxidation etching implantation diffusion silicon dopant ions            ~1000ºC

  7. SYNOPSIS Inc. TSUPREM-4 – 2-D process simulator MEDICI – 2-D device simulator TAURUS WORKBENCH – file handling environment Customer list includes: Cray Research Xerox Corp. Motorola Honeywell National Semiconductor Signetics Texas Instruments RCA Tektronix Eaton Corp.

  8. ADVANTAGES OF COMPUTER SIMULATION IN IC MANUFACTURE • LOW COST • SHORT DEVELOPMENT TIMES • (FOR DEVELOPING NEW PROCESSES • OR OPTIMIZING EXISTING ONES) • 3. YIELDS DETAILED INFORMATION

  9. Approaching the $2bn factory Fabrication cost ($m) Source: Yoshio Nishi, Vice-president Texas Instruments Year

  10. Device • structure • Structural • measurements • Doping • concentrations • Concentration • vs depth – 1-D • profile Al oxide poly-Si gate source drain

  11. Electrical properties • Output • characteristics • (IDS vs VDS) • Gate characteristic • (ID vs VG - gives VT) • Breakdown voltage VT

  12. Potential contours

  13. THE NICEWAY EXERCISE • Three 3-hour lab sessions (starting in week 7) • location – Teaching Lab C (TLC) • Session 1: Introductory • exercise • Session 2: n-channel • MOS design exercise • Session 3: p-channel • CMOS design exercise

  14. THE NICEWAY EXERCISE • PREPARATION • Read sections 1-4 of the manual before first • session. • Bring an exercise book to act as a lab-book (doesn’t have to be anything expensive, but not a loose-leaf binder). • There is a preparation sheet for session 3 that must be handed in to EETO – see last page of handout.

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