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Delay Locked Loops and Phase Locked Loops

Delay Locked Loops and Phase Locked Loops. Motivation: System. U1. U2. G1. FF2. FF1. B2. B4. B1. B3. CLK. Analysis Setup Time Calculation. The setup time at FF2 is calculated from the common point CLK. Use the maximum delay to set up FF2:D (G1 output)

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Delay Locked Loops and Phase Locked Loops

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  1. Delay Locked LoopsandPhase Locked Loops

  2. Motivation: System U1 U2 G1 FF2 FF1 B2 B4 B1 B3 CLK

  3. AnalysisSetup Time Calculation The setup time at FF2 is calculated from the common point CLK. Use the maximum delay to set up FF2:D (G1 output) Use the minimum delay to drive FF2:CLK (B4 output) To drive the data we add (max) B1 B2 FF1 (CLK -> Q) G1 FF2 (tsu) If the CLK at FF1 would occur at exactly the same time as CLK on the board, then the delays for B1 and B2 would effectively be zero. Note that this technique relies on the max delays being eliminated being greater then losing the minimum delays in the clock path.

  4. Setup Time Flow U1 U2 Use max for data path G1 FF2 FF1 B2 B4 B1 B3 CLK Use min for clock path

  5. AnalysisHold Time Calculation The hold time at FF2 is calculated from the common point CLK. Use the minimum delay to set up FF2:D (G1 output) Use the maximum delay to drive FF2:CLK (B4 output) To drive the clock we add (max) B3 B4 FF2 (th) If the CLK at FF2 would occur at exactly the same time as CLK on the board, then the delays for B3 and B4 would effectively be zero. Since the delay through U1 and U2/G1 can not be zero, then if FF2:th = 0, we can design the system as if flip-flops in U2 have a zero hold time at the device’s input pins. That is typically how we designed with “good” SSI and MSI devices.

  6. Hold Time Flow U1 U2 Use min for data path G1 FF2 FF1 B2 B4 B1 B3 CLK Use max for clock path

  7. Motivation: Clock Control • Locking to external signals • Phase control • Frequency Multiplication • Frequency Division

  8. Basic Phase Locked Loop LowPass Filter Phase Detector Voltage Controlled Osc. Analog Circuit

  9. Example: PLL Multiplication LowPass Filter Voltage Controlled Osc. Phase Detector Divide by n

  10. Example: PLL Multiplication LowPass Filter Voltage Controlled Osc. Phase Detector Divide by n Single Event Upset Heavy Ion or Proton

  11. DLL Another TechniqueGoal: System Clock Matches Clock at F-F U1 FF1 CLK Ideal 0 ns

  12. Buffer Tree Delays Not Negligible CLK FF1:CLK

  13. Buffer Tree Delays Not Negligible So Add A Delay CLK FF1:CLK Delayed CLK

  14. Buffer Tree Delays Not Negligible Add A Bit More Delay CLK FF1:CLK Delayed CLK More Delay

  15. Buffer Tree Delays Not Negligible Add Just A Bit More Delay CLK FF1:CLK Delayed CLK More Delay A Bit More

  16. What Did We Do? CLK FF1:CLK Delayed CLK More Delay A Bit More

  17. DLL Another TechniqueInsert “Proper” Delay U1 FF1 CLK Goal: Insert Delay to Make The Difference Zero If We Delay Things “Enough” To Line Up Corresponding Edges of Different Cycles.

  18. DLL Principle Of Operation Delay Line

  19. DLL Principle Of Operation Delay Line Single Event Upset Heavy Ion or Proton

  20. Manufacturers’ Selections • Actel • AX: PLL • ProAsic, ProAsic+ ??????? • Xilinx Virtex: DLL • Chip Express • QYH500: DLL • CX2000: PLL • CX3000: PLL

  21. Virtex Architecture Overview IOB = I/O Block DLL = Delay-locked loop BRAM = Block RAM (4,096 bits ea.) CLB = Configurable Logic Block

  22. Virtex DLL • Uses discrete digital delay line • Latency: 1 to 4 clock periods • 4 Quadrature phases • Can double frequency • quadruple if two DLL’s used • Divide by 1.5, 2, 2.5, 3,4,5,8, or 16 • Deskew board clock • Multiple FPGAs, other devices

  23. Board Level Clock De-Skewing Note: Can include multiple Virtex devices.

  24. Chip Express QYH500 DLL

  25. Chip Express QYH500 DLL Single Event Upset Heavy Ion or Proton

  26. AX PLL Architecture

  27. AX PLL • Fout = Fin * i / j • 1  i,j  64 • Programmable delays • 250 ps steps, Range ± 3.75 ns • Can cascade up to 8 PLLs

  28. +1.5V AX PLL: External Components Board FPGA

  29. Key Parameters • Minimum and Maximum Frequencies • Tolerance on input signals • Frequency • Jitter • Lock Time • Output Phase Offset • Output Jitter

  30. Timing Analysis CLK With a crystal clock oscillator, the time from rising edge to rising edge (or falling edge to falling edge) is quite stable, with crystal clock oscillators having relatively low jitter and good short term stability.

  31. CLK Timing Analysis Max • With DLL and PLL, one must check the jitter specifications carefully, to assure that worst-case timing must be met. • Analysis must include the time before the loop locks. • Analysis must include the effects of SEU’s on the loop’s control circuits. Min

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