System Design Challenges: Floorplanning & Power Planning in today’s large chips

System Design Challenges: Floorplanning & Power Planningin today’s large chips Amin Farmahini Farahani Instructor: Prof. S. Mehdi Fakhraie ASIC CMOS Course University of Tehran, School of ECE May 2006 This is a class presentation. All data are copy righted to respective authors & companies as listed in the references and have been used here for educational purpose only.

Outline • Introduction • FloorPlanning • Power Planning • Conclusion ASIC - University of Tehran

Introduction • Technology allows us to build chips consisting of hundreds of millions of transistors. • chips have several processors, large memories, peripherals, specific IP, and I/O. • DSM forced us applying new attentions and methods. • Design reuse—the use of pre-designed and pre-verified cores—is now the cornerstone of System Design (time to market). Fig. From [7] ASIC - University of Tehran

Motivation • Floorplanning & power planning helps avoid IR drop and electromigration problems. • The complexity of today’s designs have forced physical planning earlier in the flow. ASIC - University of Tehran

Definitions • Macro (IP, Child Block) • design unit that can reasonably be viewed as a stand-alone subcomponent of a complete design. • Subblock • a subcomponent of a macro (too small or specific to be a stand-alone design component). • Soft macro • one that is delivered as synthesizable RTL code. • Hard macro • one that is delivered as a GDSII file. It is fully designed, placed, and routed by the supplier (layout level). ASIC - University of Tehran

Standard-cell vs. Mixed-mode • Motivation: IP reuse Different blocks designed by different companies Fig. From [6] ASIC - University of Tehran

Hard Macro Placement • Poor quality hard macro placement  failure in area, freq. • As the number of logic gates and hard macro instances increases, placement becomes challenging (combination of hard macro and standard cells). • hundred hard macro instances with different sizes and shapes. ASIC - University of Tehran

Hard Macro Placement (cont.) • Some hard macros must be placed next to specific IO cells such as PLLs, DAC to allow wide connections. • normal method: pre-place and “fix” these macros in specific locations (typically side bar) • Blockages for the rest of the design. • rectilinear core area for the rest of the design. • Routing bottlenecks. • Long routes for some macros. ASIC - University of Tehran

Simultaneous Std. Cell & Macro Placement • Normal method do not result in optimized placement because both macros and standard cells are not considered simultaneously during wire-length optimization. • Normal method ensures maximal contiguous (minimally fragmented) space for std. cells, but may result in long routes. • So we need a better algorithm consider both std. cells and macros simultaneously. • Tradeoff between standard cell space fragmentation and wire-length is necessary. ASIC - University of Tehran

Two Placement • Standard cells surrounded by hard macros are unroutable; designs can be optimized to improve routablility by placement algorithms that do not create these types of areas [2]. ASIC - University of Tehran

Automated Grouping • Automated placement results (JupiterXTTM) Fig. From [2] ASIC - University of Tehran

Power Planning • Creation of the power network within a design • Power planning is integrated with the overall design flow and must be taken into account early in the design process because: • # of pads may determine physical size (pad limited). • The power structures within the core area consume physical area. • The power grid topology effects top level routability, and also placement and routing within the child blocks. • The power structure effects functionality and reliability. ASIC - University of Tehran

Simplified Power Distribution Architecture (four basic elements) Fig. From [3] ASIC - University of Tehran

Power Network Elements • Power Pad • Power Rings • Form complete rings around the periphery of the die, around individual hard macros, or inside of hierarchical blocks. • higher-level Metal layers • Power Straps/Trunks • Horizontal (strap) and vertical (trunk) metal wires placed in an array across the entire or section die. • higher level routing layers • typically uniformly distributed across the die. • Power Rails • Is used to connect the standard cell power rails together, and or power trunks. • Low level, typically metal 1. ASIC - University of Tehran

Power Rings • Floorplanning tool insert rings respecting available space in IO area. • User specify width and spacing of the rings. • rule of thumb: each side of the ring must carry a quarter of the current. divide overall power budget by four, using voltage, and current density for the metal layer determine the required width. • It is best to create power and ground rings around any hard macro IP present in the design. ASIC - University of Tehran

Power and Ground Trunks • Standard cell power rails are usually determined by the standard cell technology being used. • Power rings and standard cell power rails have very little flexibility. • straps and trunks have the most control and flexibility. • Most important means to address detailed IR drop across the power network. • A balance must be established between the need to retain routing resource for signal routes and the need to minimize IR drop. ASIC - University of Tehran

Conclusion • Reuse attitude is required. • Reuse permits complex designs. • Well designed re-usable IP components enable successful design. • Starting power integrity and floorplanning early is highly worthwhile in huge designs, because it avoids many problems in the later stages of the design flow. ASIC - University of Tehran

References • M. Keating, and P. Bricaud, “Reuse Methodology Manual for System-On-A-Chip Designs,” 3rd Ed., Kluwer Academic. • N. Kaul, and S. Kister, “Hard Macro Placement in Complex SoC Design,” Synopsys Inc., Sep. 2004, Available: www.SoCcentral.com. • R. Rodgers, K. Knapp, and C. Smith, “Floorplanning Principles,” SNUG (Synopsys User Group Conference), San Jose, 2005, Available: www.synopsys.com. • H. Piroozi, and K. Gopinathannair, “A Hierarchical Rail Analysis Flow for Multimillion Gate SoCs – Challenges and Solutions,” SNUG (Synopsys User Group Conference), San Jose, 2005, Available: www.synopsys.com. • D. Stringfellow, and K. Knapp, “Power Integrity for SoCs: Power Planning and Signoff Flows,” Synopsys Inc., Nov. 2005, Available: www.synopsys.com. • S. Adya, and I. Markov, “Combinatorial techniques for mixed mode placement,” University of Michigan, Available: www.eecs.umich.edu/~imarkov/EECS527-Win03. • JupiterIO: Concurrent Die/Package IO Planning, Synopsys Inc., 2005. • S. Idgunji, S. Lloyd, R. Mitchell, R. Spillman, and J. Young, “Design Planning Strategies to Improve Physical Design Flows—Floorplanning and Power Planning,” Synopsys Inc., Aug. 2003, Available: www.synopsys.com. • L. L. Azuara, and R. Dorsch, “Design for Reuse in embedded system design,” Available: www.iti.uni-stuttgart.de/~rainer/Lehre/SOCfCA01/Presentation9. ASIC - University of Tehran

Thanks Thanks for putting up with all my talk ?Any Question? ASIC - University of Tehran

System Design Challenges: Floorplanning & Power Planning in today’s large chips