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FFT Components: Signed 2 s Compliment Complex Multiplier

Outline. Project definitionPin assignmentsRipple Carry Adder/SubtractorMultiplierFIFOSimulation Procedures and ResultsLayouts and Final Numbers100MHz goalWhat still must be doneBar chart of schedule of tasks. Project Description. Signed 2's compliment complex multiplier. This multiplier m

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FFT Components: Signed 2 s Compliment Complex Multiplier

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    1. FFT Components: Signed 2s Compliment Complex Multiplier FDR: December 12, 2005 Shin Horiuchi David Schwarzenberg (leader)

    2. Outline Project definition Pin assignments Ripple Carry Adder/Subtractor Multiplier FIFO Simulation Procedures and Results Layouts and Final Numbers 100MHz goal What still must be done Bar chart of schedule of tasks

    3. Project Description Signed 2s compliment complex multiplier. This multiplier must be able to operate at speeds of 100MHz or faster. The output should have separate real and imaginary answers. The complex multiplier will be used in a FFT. This FFT will also require the use of the same complex adder and subtractor used to construct the multiplier.

    4. Project Objectives Obtain further knowledge of CMOS VLSI design. To gain experience working in teams, and with other teams. To document the design process in a professional manner, producing a final, public document.

    5. Gajski Diagram

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