Paging

1. Paging CS-502 Operating Systems CS502 Spring 2006

2. Paging • A different approach • Addresses all of the issues of previous topic • Introduces new issues of its own CS502 Spring 2006

3. CPU Logical Addresses MMU Physical Addresses Memory I/O Devices Memory Management – Review • Virtual (or logical) address vs. Physical addresses • Memory Management Unit (MMU) • Set of registers and mechanisms to translate virtual addresses to physical addresses • Processes (and CPU) see virtual addresses • Virtual address space is same for all processes, usually 0 based • Virtual spaces are protected from other processes • MMU and devices see physical addresses CS502 Spring 2006

4. Logical Address Space (virtual memory) physical memory page 0 frame 0 page 1 frame 1 page 2 frame 2 MMU page 3 … … frame Y page X Paging • Solve fragmentation problems, internal and external • Use fixed size units in both physical and virtual memory • Provide sufficient MMU hardware to allow units to be scattered across memory • Make it possible to leave infrequently used parts of virtual address space out of physical memory CS502 Spring 2006

5. Paging • Processes see a contiguous virtual address space • Memory Manager divides the virtual address space into equal sized pieces called pages • Memory Manager divides the physical address space into equal sized pieces called frames • Frame size usually a power of 2 between 512 and 8192 bytes • Frame table • One entry per frame of physical memory • State • Free • Allocated – process(es) • sizeof(page) = sizeof(frame) CS502 Spring 2006

6. Paging – Address Translation • Translating virtual addresses • a virtual address has two parts: virtual page number & offset • virtual page number (VPN) is index into a page table • page table entry contains page frame number (PFN) • physical address is: startof(PFN) + offset • Page tables • Supported by MMU hardware • Managed by the Memory Manager • Map virtual page numbers to page frame numbers • one page table entry (PTE) per page in virtual address space • i.e., one PTE per VPN CS502 Spring 2006

7. Paging Translation logical address virtual page # offset physical memory page frame 0 page table page frame 1 physical address page frame 2 page frame # F(PFN) offset page frame 3 … page frame Y CS502 Spring 2006

8. Page Translation Example • Assume a 32 bit address space • Assume page size 4KB (log2(4096) = 12 bits) • For a process to address the full logical address space • Need 220 PTEs – VPN is 20 bits • Offset is 12 bits • Translation of virtual address 0x12345678 • Offset is 0x678 • Assume PTE(12345) contains 0x01000 • Physical address is 0x01000678 CS502 Spring 2006

9. 1 1 1 2 20 V R M prot page frame number PTE Structure • Valid bit gives state of this PTE • says whether or not a virtual address is valid – in memory and VA range • If not set, page might not be in memory or may not even exist! • Reference bit says whether the page has been accessed • it is set by hardware when a page has been read or written to • Modify bit says whether or not the page is dirty • it is set by hardware on every write to the page • Protection bits control which operations are allowed • read, write, etc. • Page frame number (PFN) determines the physical page • physical page start address • Other bits dependent upon machine architecture CS502 Spring 2006

10. Paging – Advantages • Easy to allocate physical memory • pick any free frame • No external fragmentation • All frames are equal • Easy to swap out pages (called pageout) • Size is usually a multiple of disk blocks • PTE contains info that helps reduce disk traffic • Processes can run with not all pages swapped in CS502 Spring 2006

11. Definition — Page Fault • A trap when a process attempts to reference a virtual address of a page not in physical memory • Valid bit in PTE is set to false • If page exists on disk:– • Suspend process • If necessary, throw out some other page (update its PTE) • Swap in desired page, resume execution • If page does not exist on disk:– • Return program error or • Conjure up a new page and resume execution • E.g., for growing the stack! CS502 Spring 2006

12. Paging Observations • Recurring themes in paging • Temporal Locality – locations referenced recently tend to be referenced again soon • Spatial Locality – locations near recent references tend to be referenced soon • Definitions • Working set: The set of pages that a process needs to run without frequent page faults • Thrashing: Excessive page faulting due to insufficient frames to support working set CS502 Spring 2006

13. Paging Issues • Minor issue – internal fragmentation • Memory allocation in units of pages (also file allocation!) • #1 — Page Tables can consume large amounts of space • If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space -> 4MB for each process’s page table • What happens for 64-bit logical address spaces? • #2 — Performance Impact • Converting virtual to physical address requires multiple operations to access memory • Read Page Table Entry from memory! • Get page frame number • Construct physical address • Assorted protection and valid checks • Without fast hardware support, requires multiple memory accesses and a lot of work per logical address CS502 Spring 2006

14. Issue #1: Page Table Size • Process Virtual Address spaces • Not usually full – don’t need every PTE • Processes do exhibit locality – only need a subset of the PTEs • Two-level page tables • Virtual Addresses have 3 parts • Master page number – points to secondary page table • Secondary page number – points to PTE containing page frame # • Offset • Physical Address = offset + startof (PFN) • Note: Master page number can be used as Segment # • previous topic • n-level page tables are possible, but rare in 32-bit systems CS502 Spring 2006

15. Two-level page tables virtual address master page # secondary page# offset physical memory page frame 0 master page table physical address page frame 1 page frame # offset secondary page table # secondary page table # addr page frame 2 page frame 3 page frame number … page frame Y CS502 Spring 2006

16. Multilevel Page Tables • Sparse Virtual Address space – very few secondary PTs ever needed • Process Locality – only a few secondary PTs needed at one time • Can page out secondary PTs that are not needed now • Don’t page Master Page Table • Save physical memory However • Performance is worse • Now have 3 memory access per virtual memory reference or instruction fetch • How do we get back to about 1 memory access per VA reference? • Problem #2 of previous slide CS502 Spring 2006

17. Paging Issues • Minor issue – internal fragmentation • Memory allocation in units of pages (also file allocation!) • #1 — Page Tables can consume large amounts of space • If PTE is 4 bytes, and use 4KB pages, and have 32 bit VA space -> 4MB for each process’s page table • What happens for 64-bit logical address spaces? • #2 — Performance Impact • Converting virtual to physical address requires multiple operations to access memory • Read Page Table Entry from memory! • Get page frame number • Construct physical address • Assorted protection and valid checks • Without fast hardware, requires multiple memory accesses and a lot of work per logical address CS502 Spring 2006

18. VPN # Frame # Associative Memory(aka Dynamic Address Translation) • Do fast hardware search of all entries in parallel for VPN • If present, use PFN directly • If not, • Look up in page table (multiple accesses) • Load VPN and PFN into Associative Memory (throwing out another entry as needed) CS502 Spring 2006

19. Translation Lookaside Buffer (TLB) • Associative memory implementation in hardware • Translates VPN to PTE (containing PFN) • Done in single machine cycle • TLB is hardware assist • Fully associative – all entries searched in parallel with VPN as index • Returns PFN • MMU use PFN and offset to get Physical Address • Locality makes TLBs work • Usually have 8–1024 TLB entries • Sufficient to deliver 99%+ hit rate (in most cases) • Works well with multi-level page tables CS502 Spring 2006

20. MMU with TLB CS502 Spring 2006

21. Memory Memory Memory I/O device I/O device I/O device I/O device Typical Machine Architecture CPU MMU and TLBlive here Bridge Graphics CS502 Spring 2006

22. TLB-related Policies • OS must ensure that TLB and page tables are consistent • When OS changes bits (e.g. protection) in PTE, it must invalidate TLB copy • If dirty bit is set, write back to page table entry • TLB replacement policies • Random • Least Recently Used (LRU) – with HW help • What happens on context switch? • Each process has own page tables (multi-level) • Must invalidate all TLB entries • Then TLB fills as new process executes • Expensive context switches just got more expensive! • Note benefit of Threads CS502 Spring 2006

23. Alternative Page Table format – Hashed • Common in address spaces > 32 bits. • The virtual page number is hashed into a page table. This page table contains a chain of VPNs hashing to the same value. • Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted • Still uses TLB for execution CS502 Spring 2006

24. Hashed Page Tables CS502 Spring 2006

25. Alternative Page Table format – Inverted • One entry for each real page of memory. • Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page. • Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. • Use hash table to limit the search to one or a few page-table entries. • Still uses TLB for execution CS502 Spring 2006

26. Inverted Page Table Architecture CS502 Spring 2006

27. Paging – Some Tricks • Shared Memory • Part of virtual memory of two or more processes map to same frames • Finer grained sharing than segments • Data sharing with Read/Write • Shared libraries with eXecute • Each process has own PTEs – different privileges • Copy-on-write (COW) – e.g. on fork() • Don’t copy all pages – create shared mapping of parent pages in child • Make shared pages read-only in child • When child does write, a protection fault occurs • OS copies the page and resumes client CS502 Spring 2006

28. Paging – More Tricks • Memory-mapped files • Instead of standard system calls (read(), write(), etc.) map file starting at virtual address X • I.e., use the file for swap space for that part of VM • Access to “X + n” refers to file at offset n • All mapped file PTEs marked at start as invalid • OS reads from file on first access • OS writes to file when page is dirty and page is evicted CS502 Spring 2006

29. Paging – Summary • Partition virtual memory into equal size units called pages • Any page can fit into any frame in physical memory • No relocation needed by loader • Only active pages in memory at any time • Supports very large virtual memories and segmentation • Hardware assistance is essential • First introduction to the fundamental principle of caching CS502 Spring 2006

30. Caching • The act of keeping a small subset of active items in fast storage while most of the items are in much larger, slower storage • Virtual Memory • Very large, mostly stored on (slow) disk • Small working set in (fast) RAM during execution • Page tables • Very large, mostly stored in (slow) RAM • Small working set stored in (fast) TLB registers CS502 Spring 2006

31. Caching is Ubiquitous in Computing • Transaction processing • Keep records of today’s departures in RAM while records of future flights are on disk • Program execution • Keep the bytes near the current program counter in on-chip memory while rest of program is in RAM • File management • Keep disk maps of open files in RAM while retaining maps of all files on disk • … CS502 Spring 2006

32. Caching issues • When to put something in the cache • What to throw out to create cache space for new items • How to keep cached item and stored item in sync after one or the other is updated • How to keep multiple caches in sync across processors or machines • Size of cache needed to be effective • Size of cache items for efficiency • … CS502 Spring 2006