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# Lava II

Lava II. Mary Sheeran , Koen Claessen Chalmers University of Technology Satnam Singh, Xilinx. In file Lecture1.hs (reminder). import Lava fa (cin,(a,b)) = (sum,cout) where part_sum = xor2(a,b) sum = xor2(part_sum,cin) cout = mux(part_sum,(a,cin))

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## Lava II

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1. Lava II Mary Sheeran, Koen Claessen Chalmers University of Technology Satnam Singh, Xilinx

2. In file Lecture1.hs (reminder) import Lava fa (cin,(a,b)) = (sum,cout) where part_sum = xor2(a,b) sum = xor2(part_sum,cin) cout = mux(part_sum,(a,cin)) Main> simulate fa (high,(high,high)) (high,high)

3. import Lava Import Arithmetic import Patterns component as parameter bAdder fadd as = ss ++ [c] where (ss,c) = rowfadd (zero, as) connection pattern

4. Main> simulate (bAdder fa) [(high,low),(low,high),(low,high)] [high,high,high,low] the circuit Main> simulate (bAdder fa) (replicate 8 (high,low)) [high,high,high,high,high,high,high,high,low] lsb

5. Simple delay analysis fAddI (a1s, a2s, a3s, a1c, a2c, a3c) (a1,(a2,a3)) = (s,cout) where s = max (a1s+a1) (max (a2s+a2) (a3s+a3)) cout = max (a1c+a1) (max (a2c+a2) (a3c+a3)) fI :: (Signal Int,(Signal Int, Signal Int)) -> (Signal Int, Signal Int) fI as = fAddI (20,20,10,10,10,10) as

6. Main> simulate fI(10,(12,12)) (32,22) Main> simulate (bAdder fI)(replicate 8 (0,0)) [20,30,40,50,60,70,80,90,80] Note that simulate takes 2 arguments, the circuit and the input Main> :t (bAdder fI) bAdder fI :: [(Signal Int,Signal Int)] -> [Signal Int]

7. Main> simulate bin2int (replicate 8 high) 255 Main> simulate (int2bin 8) 5 [high,low,high,low,low,low,low,low]

8. bAdd fadd (as,bs) = ss ++ [c] where (ss,c) = row fadd (zero, zip as bs) wrap n badd (a,b) = s where s = bin2int (badd (int2bin n a, int2bin n b))

9. Combinator style wrap1 n badd = (int2bin n -|- int2bin n) ->- badd ->- bin2int

10. Main> simulate (wrap1 8 (bAdd fa)) (12,14) 26 Would like (wrap n (bAdd fa)) to be the same as built in plus (the built in (abstract) circuit for integer addition) Tempting to try formal verification, but only Boolean formal verification available in Lava right now! (Aside: reasoning about arithmetic is HARD) Instead, program some tests

11. In the file addCheck n = prop_Equivalent (wrap n (bAdd fa)) plus And then at the prompt: Main> simulate (addCheck 8) (13,17) high

12. sim0 = simulate (map (addCheck 4) ->- andl) [(a,b) | a <- range, b <- range] Main> sim0 high

13. In the file sim1 n = simulate (map (addCheck n) ->- andl) [(a,b) | a <- range, b <- range] where range = map int [0 .. (2^n-1)] And then at the prompt: Main> :t int int :: Int -> Signal Int Main> sim1 4 high

14. Getting it wrong Main> simulate bAdder fa (replicate 8 (high,low))

15. Unfortunate error message  ERROR - Unresolved overloading *** Type : Generic ([(Signal Bool,Signal Bool)] -> [Signal Bool]) => [Signal Bool] *** Expression : simulate bAdder fa (replicate 8 (high,low)) You will always get this if you give simulate too many arguments Down side of embedded language. See Lava intro on course page for some typical error messages. Mail us if you get stuck.

16. Style hints dStudcct a b = outs where ....and2(a,b)... This is perfectly correct, but it means I have to go looking among the parameters to see which are the circuit inputs. GATHER them into a single structure, which should be last (rightmost) input. Then I can easily tell what the interface of the circuit is. mycct (a,b) = outs ......

17. Style hints More generally, have circuit parameters as separate inputs, followed by all circuit inputs in one structure (tuple or list, possibly nested). ”the input” cctName p1 p2 (a,bs) = (ds,e) .... used to control generation. For example integer to control size. Or constants for use in the circuit (see next example). Usually have zero or one parameters.

18. Register reg init (w,din) = dout where dout = delay init m m = mux (w,(dout,din))

19. Register parameter reg init (w,din) = dout where dout = delay init m m = mux (w,(dout,din))

20. Register reg init (w,din) = dout where dout = delay init m m = mux (w,(dout,din)) Main> reg low (high,high) …. orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,h igh],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[hig h],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[ andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],a ndl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],del ay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[h igh,high],andl[inv[high],delay[low,orl[andl[high,high],andl[inv[high],delay[low,orl[andl[high,high],andl[in v[{Interrupted!}

21. Register This is why we have a two stage process. First make internal representation in a data type and THEN simulate or generate formats. the circuit Main> simulateSeq (reg low) [(high,low),(low,high),(high,high),(low,high)] [low,low,low,high]

22. Sequential circuits MUST be simulated using simulateSeq Main> simulate (reg low) (high,high) Program error: evaluating a delay component

23. Avoid non-circuits! notcirc (a,b) = if (a==high) then b else inv b Should be able to find out circuit structure without knowing VALUES of the inputs Use MUX

24. Working on lists g f parl f g = halveList ->- (f -|- g) ->- append

25. two f f f

26. f f f f two (two f)

27. Many twos twoN 0 circ = circ twoN n circ = two (twoN (n-1) circ)

28. Interleave f f ilv f unriffle ->- two f ->- riffle

29. Many interleaves ilv (ilv (ilv C))

30. Many interleaves ilvN 0 circ = circ ilvN n circ = ilv (ilvN (n-1) circ)

31. Wiring id2 swap

32. Butterfly bfly circ bfly circ

33. Defining Butterfly bfly 0 circ = id bfly n circ = ilvN (n-1) circ ->- two (bfly (n-1) circ)

34. Defining Butterfly Connection pattern parameter circuit bfly 0circ = id bfly n circ = ilvN (n-1) circ ->- two (bfly (n-1) circ)

35. Another style (matter of taste) bflly 0 circ as = as bflly n circ as = os where bs = ilvN (n-1) circ as os = two (bflly (n-1) circ) bs

36. Butterfly Layout on an FPGA

37. mergers and sorters Butterfly of two-input two-output comparators is merger binary or complex numbers, or even on bit-serial numbers ( Batcher’s bitonic sorter) Such a sorting network is correct if it sorts BITs (theorem known as the 0-1 principle)

38. Means we can plug in bit-sorters and check the property that the output is always sorted using a SAT-solver or SMV. (Another example of a non-standard component, and of squeezing a difficult problem (integer sorting) into an easier one (bit sorting)) FFT is based on similar recursive structure

39. Notes Generic circuits and connection patterns easy to describe (the power of Haskell) Gives high degree of reuse Verify FIXED SIZE circuits (squeezing the problem down into an easy enough one)

40. Next lecture More examples Use of non-standard interpretation DURING circuit generation

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