組合邏輯的函數 Functions of Combination Logic

Chapter 6 組合邏輯的函數Functions of Combination Logic • 基本的加法器 • 並聯二進位加法器 • 比較器 • 解碼器 • 編碼器 • 轉碼器 • 多工器(資料選擇器) • 解多工器 • 同位元產生/檢查器 • 檢修 • 可程式邏輯 • 12. 以VHDL編寫邏輯函數的程式

1. 基本的加法器 半加法器 Figure 6--1 Logic symbol for a half-adder(半加器). Thomas L. FloydDigital Fundamentals, 8e

1. 基本的加法器 Figure 6--2 Half-adder logic diagram. Thomas L. FloydDigital Fundamentals, 8e

1. 基本的加法器 全加法器 Figure 6--3 Logic symbol for a full-adder (全加器). Thomas L. FloydDigital Fundamentals, 8e

1. 基本的加法器 Figure 6--4 Full-adder logic. Open file F06-04 to verify operation. Thomas L. FloydDigital Fundamentals, 8e

Figure 6--5 Full-adder implemented with half-adders. 以2個半加器來實做全加器 Thomas L. FloydDigital Fundamentals, 8e

1. 基本的加法器 例題 6-1 求圖 6-6 所示的三個全加器的輸出圖 6-6 Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 Figure 6--7 Block diagram of a basic 2-bit parallel adder using two full-adders. Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 Figure 6-8 根據公式計算一下答案！例題 6-2 如圖6-8所示，當輸入的二進位數為101與011時，試求此3位元平行加法器的總合與進位輸出。 Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 Figure 6--9 A 4-bit parallel adder. 四位元平行加法器 Thomas L. FloydDigital Fundamentals, 8e

進位傳遞(carry propagation) 進位產生進位傳遞

進位遞迴產生器 C0=輸入進位 C1=G0+P0C0 C2=G1+P1C1=G1+P1G0+P1P0C0 C3=G2+P2C2=G2+P2G2+P1P2G0+P2P1P0C0

2. 二進位平行加法器 Figure A--2 Four-bit parallel adders. Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 Figure A--3 Characteristics for the 74LS283. pp. A-3 Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器

四位元預見進位產生器

2. 二進位平行加法器 Figure 6--10 Examples of adder expansion. Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 Figure 6--11 Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses). 例題6-4 將兩個四位元平行加法器，連接成八位元平行加法器，求輸入下列數值後，所產生之輸出位元 Thomas L. FloydDigital Fundamentals, 8e

2. 二進位平行加法器 應用範例：簡單投票系統 Figure 6--12 A voting system using full-adders and parallel binary adders. Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 Figure 6--13 Basic comparator operation. 相等輸出 Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 Figure 6--14 Logic diagram for equality comparison of two 2-bit numbers. Open file F06-16 to verify operation. Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 Figure 6--15 例題6-5 求下列電路的輸出 Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 不相等輸出 1-bit comparator Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 0 1 0 2-bit comparator Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 Figure 6--16 Logic symbol for a 4-bit comparator with inequality indication. Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 例題 6-6 求 Figure 6—17 的輸出 Thomas L. FloydDigital Fundamentals, 8e

3. 比較器 Figure A--4 Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses). pp. A-4 Thomas L. FloydDigital Fundamentals, 8e

3. 比較器

3. 比較器 Figure 6--19 An 8-bit magnitude comparator using two 74HC85s. Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure 6--20 Decoding logic for the binary code 1001 with an active-HIGH output. 基本的二進制解碼器 Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure 6--21 Decoding logic for producing a HIGH output when 1011 is on the inputs. 例題6-8 試設計一個解碼器, 使得當輸入二進碼1011時, 輸出High Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure 6--22 Logic symbol for a 4-line-to-16-line (1-of-16) decoder. Open file F06-24 to verify operation. 四位元解碼器 Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure A—5a,b Pin diagram and logic symbol for the 74HC154 1-of-16 decoder. pp. A-5 Thomas L. FloydDigital Fundamentals, 8e

Figure A—5c Pin diagram and logic symbol for the 74HC154 de-multiplexer. pp. A-5 解多工器 CS1=0 輸出為沒作用 CS1=1 輸出由選擇線選到的為Low Data selector Data input Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 例題 6-9 某個應用電路需用五位元數值進行解碼，試使用兩個4對16線解碼器實作。 Figure 6--23 A 5-bit decoder using 74HC154s. Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 應用範例：電腦輸入輸出裝置的選擇 Figure 6--24 A simplified computer I/O port system with a port address decoder with only four address lines shown. Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 例題 6-10 BCD轉十進位解碼器的邏輯圖如圖6-25，如果將圖6-26(a)的輸入波形施加到輸入端，求其輸出波形？ Figure 6--25 The 74HC42 BCD-to-decimal decoder. Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure 6--26 Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure 6--27 Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs. Open file F06-30 to verify operation. BCD轉7段顯示解碼器 Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure A--6 Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver. pp. A-5 BI=Blank Input RBI=Ripple BI RBO=Ripple Blank Output Light Test Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure A—7a Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6 Ripple Blanking (消零) 的用法 Thomas L. FloydDigital Fundamentals, 8e

4. 解碼器 Figure A—7b Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver. pp. A-6 Ripple Blanking (消零) 的用法 Thomas L. FloydDigital Fundamentals, 8e

5. 編碼器 Figure 6--28 Logic symbol for a decimal-to-BCD encoder. 十進位轉BCD編碼器 Thomas L. FloydDigital Fundamentals, 8e

Figure 6--29 Basic logic diagram of a decimal-to-BCD encoder. 沒有優先權編碼的缺點：兩輸入同時active會出錯 A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs. Thomas L. FloydDigital Fundamentals, 8e

編碼器 • 編碼器:解碼器的反函數 • 8到3優先權編碼器:

8到3優先權編碼器 c=y7y6y5y4y3y2y1+y7y6y5y4y3+y7y6y5+y7 =y7+y6y5+y6y4y3+y6y4y2y1 b=y7y6y5y4y3y2+y7y6y5y4y3+y7y6+y7 =y7+y6+y5y4y3+y5y4y2 a=y7y6y5y4+y7y6y5+y7y6+y7 =y7+y6+y5+y4

8到3優先權編碼器 y7 y6 y5 y4 y3 y2 y1 y0 a b c

Figure A--8 Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority). pp. A-7 10進位轉BCD編碼器 Thomas L. FloydDigital Fundamentals, 8e

5. 編碼器 Figure A--9 Logic symbol for the 74F148 8-line-to-3-line encoder. pp. A-8 8對3線編碼器 No Input Low  EO=low EI=Low  At least one Input Low  GS=low Thomas L. FloydDigital Fundamentals, 8e

5. 編碼器 Figure A--10 A 16-line-to-4 line encoder using 74F148s and external logic. pp. A-8 8~15 pin No Input Low  EO=low EI=Low  At least one Input Low  GS=low Thomas L. FloydDigital Fundamentals, 8e

組合邏輯的函數 Functions of Combination Logic