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ASIC Implementation for ‘Internet of Everything’ devices

ASIC Implementation for ‘Internet of Everything’ devices. Dec 2012. Overview. Requirements – energy budget Requirements – energy consumed Balance - energy consumed against budget Implementation challenges Implementation techniques. Power Requirements.

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ASIC Implementation for ‘Internet of Everything’ devices

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  1. ASICImplementation for ‘Internet of Everything’ devices Dec 2012

  2. Overview • Requirements – energy budget • Requirements – energy consumed • Balance - energy consumed against budget • Implementation challenges • Implementation techniques

  3. Power Requirements • Interconnected devices can help make residential and commercial building more energy efficient. • In order to have overall energy reduction, the collection of interconnected devices must themselves be very energy efficient. • For Line powered devices < 1 mW average power is good enough. • For battery powered device, the battery replacement interval must be considered. • The most common low cost batteries are alkaline AAA and AA, and coin cell. • Two AAA batteries contains 7500 Joules of useable energy. In order to last 2 years, average power must be below 120uW. • A CR2450 coin cell battery contains 4300 Joules useable energy. In order to last 2 years, average power must be below 70uW.

  4. Interconnected device Capabilities

  5. Efficient Activation • Major tasks consume much more energy than target power level. • Typically, while tasks are running power is 300mW. • Duty cycling to a lower standby current is critical to achieving lower • Standby power with state retention bring power level down to 30uW • Duty cycle of 10,000 : 1 corresponds to 6 ms of activity every 1 minute • Device to cloud centric use cases are simpler, transmit can be asynchronous. • Cloud to device centric use cases have latency and availability implications with this duty cycling. • Device can poll for data • Device can be synchronized with network and listen of data at specific intervals

  6. Challenges for Silicon Implementation • Market demands lower cost of smaller process nodes, but this drives leakage currents higher. • Higher level of integration is required in these small interconnected devices, which requires combining RF process with logic process and non volatile memory processes. • For some sensing and control applications, higher voltages (12 V) are also required. • Requirement for TCP/IP cloud connectivity increases memory footprint and non-volatile storage requirements which increases leakage.

  7. Low Power Silicon Implementation Strategies

  8. Advancements in Communication ASICefficiency and silicon implementation • Duty cycling advancements • protocols such as 802.11 are adding support for connected devices in longer duration standby state. • low latency startup and fast return to suspend state • Active power advancements • 900 MHz band enables longer range and lower power receive and transmit. • Standby power advancements • multiple power islands, with separate high efficient regulator for always on circuits. • Segregated RAM with separate power collapse regions and non volatile regions • fine grain power gating to minimize leakage from logic in standby state

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