Edge Detection Using a FIR Filter

1. Scott Robinson Aaron Sikorski Peter Phelps Edge Detection Using a FIR Filter

2. Outline • Introduction • FIR Filter Design • Optimization • Application • Edge Detection • Sobel Filter • Communications • Design Process Flow • Conclusion

3. Introduction • Goal: Improve and apply our previously designed FIR Filter for a specific purpose. Implement design on NEXYS2 FPGA. • Requirements: The FPGA must communicate with a host PC through the USB interface.

4. FIR Filter Design • N-bit input values, M-bit tap values, K-bit taps • Modulated such that the Booth encoding and Wallace tree were both in a single module.

5. Optimization of Filter Design • Removed unnecessary pipelining in our full-adder module. • Changed our Booth constants to be generated on the tap values. • Moved the Booth encoding to outside of the Multiplier module. • Greatly reduced the area required while not sacrificing any speed by minimizing the replication of logic.

6. Changes in Logic Tap 1 … Tap K Input [t] Input [t-K] Old Design New Design Booth Encoder Multiplier K Multiplier 1 Input [t] Input [t-K] Booth Encoder Booth Encoder … … Multiplier 1 Multiplier K Partial Product Generator Partial Product Generator Partial Product Generator Partial Product Generator Wallace Tree Wallace Tree Wallace Tree Wallace Tree

7. Measures of Improvement Old Design: New Design:

8. Application – Edge Detection • Description of edge detection and why we chose it. Why is it important?

9. Edge Detection in MATLAB • What we used matlab for.

10. Sobel Filter • Stucture of sobel filter. • Add a picture.

11. Communications – FPGA • Verilog code based on usbif_reg. • Uses a state machine to control input/output. • Instantiates a single Sobel filter. • Logic flow: • Store input into register array • Step inputs through Sobel filterand store output into separate register array • Output register array

12. Communications – Host PC • Uses C code which is based on usb_demo. • Sends sixty bytes continuously until EOF. • Stored the output of the FPGA into an array which is reconstructed into an image in MATLAB. • Note: Initial design sent and received one byte at a time which caused our design to be too slow. Once changing to the “sixty input – 20 output” design our speed reduced to under three minutes.

13. Design Process Flow

14. Thank You Questions?