ELEC 7770 Advanced VLSI Design Spring 2007 Power Consumption in a Memory

1. ELEC 7770Advanced VLSI DesignSpring 2007Power Consumption in a Memory Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07 ELEC 7770: Advanced VLSI Design (Agrawal)

2. Memory Architecture M bits M bits S0 S0 Word 0 Word 0 Word 1 Word 1 Storage cell Storage cell Word 2 Word 2 A0 A1 . Ak-1 N words Decoder k address lines N words Word N-2 Word N-2 Word N-1 Word N-1 SN-1 SN-1 k = log2N Input-Output (M bits) Input-Output (M bits) ELEC 7770: Advanced VLSI Design (Agrawal)

3. Memory Organization Bit line 2L-K Storage cell AK AK-1 AL-1 Word line M.2K Sense amplifiers/drivers A0 AK-1 Column decoder Input-Output (M bits) ELEC 7770: Advanced VLSI Design (Agrawal)

4. An SRAM Cell WL VDD bit bit BL BL ELEC 7770: Advanced VLSI Design (Agrawal)

5. Read Operation 1. Precharge to VDD 2. WL = Logic 1 WL VDD bit bit BL BL 3. Sense amplifier converts BL swing to logic level ELEC 7770: Advanced VLSI Design (Agrawal)

6. Precharge Circuit VDD VDD PC WL VDD bit bit BL BL Diff. sense ampl. ELEC 7770: Advanced VLSI Design (Agrawal)

7. Reading 1 from Cell WL BL Precharge BL Sense ampl. output time ELEC 7770: Advanced VLSI Design (Agrawal)

8. Write Operation, bit = 1→ 0 2. WL = 1 WL VDD bit bit BL BL 0 1 1. Set BL = 0, BL = 1 ELEC 7770: Advanced VLSI Design (Agrawal)

9. Cell Array Power Management • Smaller transistors • Low supply voltage • Lower voltage swing (0.1V – 0.3V for SRAM) • Sense amplifier restores the full voltage swing for outside use. ELEC 7770: Advanced VLSI Design (Agrawal)

10. Sense Amplifier VDD Full voltage swing output bit bit SE Sense ampl. enable: Low when bit lines are precharged and equalized ELEC 7770: Advanced VLSI Design (Agrawal)

11. Block-Oriented Architecture • A single cell array may contain 64 Kbits to 256 Kbits. • Larger arrays become slow and consume more power. • Larger memories are block oriented. ELEC 7770: Advanced VLSI Design (Agrawal)

12. Hierarchical Organization Block 0 Block 1 Block P-1 Row addr. Column addr. Block addr. Global data bus Control circuitry Global amplifier/driver Block selector I/O ELEC 7770: Advanced VLSI Design (Agrawal)

13. Power Saving • Block-oriented memory • Lengths of local word and bit lines are kept small. • Block address is used to activate the addressed block. • Unaddressed blocks are put in power-saving mode: • sense amplifier and row/column decoders are disabled. • Power is maintained for data retention in cells. ELEC 7770: Advanced VLSI Design (Agrawal)

14. Static Power 1.3μ 1.1μ 900n 700n 500n 300n 100n 8-kbit SRAM 0.13μ CMOS Leakage current (Amperes) 7x increase 0.18μ CMOS 0.0 0.6 1.2 1.8 Supply voltage ELEC 7770: Advanced VLSI Design (Agrawal)

15. Adding Resistance in Leakage Path VDD Low-threshold transistor sleep VDD.int SRAM cell array SRAM cell array SRAM cell array VSS.int sleep GND ELEC 7770: Advanced VLSI Design (Agrawal)

16. Lowering Supply Voltage VDD VDDL= 100mV for 0.13μ CMOS Sleep = 1, data retention mode sleep SRAM cell array SRAM cell array SRAM cell array GND ELEC 7770: Advanced VLSI Design (Agrawal)

17. Mem 1 instr. A instr. C instr. E . . . f/2 Parallelization of Memories Mem 2 instr. B instr. D instr. F . . . Power = C’ f/2 VDD2 f/2 0 MUX 1 f/2 C. Piguet, “Circuit and Logic Level Design,” pp. 124-125 in W. Nebel and J. Mermet (Eds.), Low Power Design in Deep Submocron Electronics, Springer, 1997. ELEC 7770: Advanced VLSI Design (Agrawal)

18. References • K. Itoh, VLSI Memory Chip Design, Springer-Verlag, 2001. • J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, Inc., 2003. ELEC 7770: Advanced VLSI Design (Agrawal)