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Requirements for Models of Achievable Routing

Requirements for Models of Achievable Routing. Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent Univ. Supported by Cadence Design Systems, Inc. and the MARCO Gigascale Silicon Research Center. Outline. Models of achievable routing Review of existing models

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Requirements for Models of Achievable Routing

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  1. Requirements for Models ofAchievable Routing Andrew B. Kahng, UCLA Stefanus Mantik, UCLA Dirk Stroobandt, Ghent Univ. Supported by Cadence Design Systems, Inc. and the MARCO Gigascale Silicon Research Center ISPD 2000, San Diego

  2. Outline • Models of achievable routing • Review of existing models • Validation of models through experiments! • Experimental analysis of assumptions • Future model requirements • Conclusions ISPD 2000, San Diego

  3. Models of achievable routing • wirelength estimation models (Donath, …) • actual placement information • Required versus available resources • Required versus available resources ISPD 2000, San Diego

  4. Models of achievable routing • Required versus available resources limited by routing efficiency factor hr ISPD 2000, San Diego

  5. Models of achievable routing • Required versus available resources limited by power/ground (signal net fraction si) ISPD 2000, San Diego

  6. Models of achievable routing • Required versus available resources limited by via impact factor vi (ripple effect) utilization factor Ui(available / supplied area) ISPD 2000, San Diego

  7. Use of achievable routing models • Optimizing interconnect process parameters for future designs (number of layers, wire width and pitch per layer, ...) • With given layer characteristics: predict the number of layers needed • If number of layers fixed: oracle “(not) routable!” (SUSPENS, GENESYS, RIPE, BACPAC, GTX) • Supplying objectives that guide layout tools to promising solutions (wire planning) ISPD 2000, San Diego

  8. Validation is key • Models must be accurate, must support empirical verification and calibration • No existing model is validated with real place-and-route data • Our work concentrates on validation: • understanding reasons for validation gap • processes for model validation • improvements needed in future models ISPD 2000, San Diego

  9. Review of existing models • Sai-Halasz [Proc. IEEE, 1995] • power/ground: si 20% • routing efficiency: hr = 40% • via impact: each layer blocks 15% on layers below with same pitch • model is widely used • model is rather pessimistic ISPD 2000, San Diego

  10. } V tier H } V tier H Review of existing models (cont.) • Chong and Brayton [SLIP, 1999] • layer assignment model • layer pairs form tiers (H and V) • wires are routed on 1 tier • shorter wires on lower tiers • available resources model • constant routing efficiency for all layers: hr = 65% • via impact factor vi based on actual via area • each wire uses 2 via stacks (block wires on lower layers) • total number of wires per layer (thus vias) defined by layer assignment model ISPD 2000, San Diego

  11. } V tier H } V tier H tracks Review of existing models (cont.) • Chen et al. [private communication, 1999] • layer assignment model similar to Chong’s • available resources model • constant routing efficiency (40% < hr < 66%) • via impact model • terminal vias and turn vias • each wire uses 2 via stacks • number of terminal vias defined by layer assignment model • sparse via model = Chong • dense via model: give up 1 track every X tracks • results in via impact proportional to sqrt(Chong’s impact factor) ISPD 2000, San Diego

  12. 70 Sai-Halasz (M4) 65 Chong 60 Sai-Halasz (M3) 55 Chen 50 Sai-Halasz (M2) 45 40 Sai-Halasz (M1) 35 Model validation • Models can be validated only by testing against comparable experimental results • none of reviewed models was validated • even simple comparison: huge differences Utilization factor/layer (%) Via fill rate (%) 0 1 3 4 5 ISPD 2000, San Diego

  13. 75 Sai-Halasz (M4) Exp M3 70 Chong 65 Exp M4 Sai-Halasz (M3) 60 Chen 55 Utilization factor (%) Sai-Halasz (M2) 50 45 Sai-Halasz (M1) 40 Exp M2 35 30 0 1 2 3 4 5 6 Via fill rate (%) Model validation (cont.) • Experimental validation • ensure congested design • Experimental validation • Typical industry standard-cell block design • 42.000 cells, 1999, 5 layers • Cadence placement and gridded routing tools • same pitch (1 mm) for all layers • via size .62 mm • all pins for cells are on M1 ISPD 2000, San Diego

  14. 75 Sai-Halasz (M4) 70 Chong Exp M3 65 Sai-Halasz (M3) 60 Chen 55 Utilization factor (%) Sai-Halasz (M2) 50 Exp M4 45 Sai-Halasz (M1) 40 Exp M2 35 30 0 1 2 3 4 5 6 Via fill rate (%) Model validation (cont.) • Experimental validation • adding virtual vias on M3 and M4 (effect of wires on virtual upper layers) ISPD 2000, San Diego

  15. 80 70 60 50 Chong 40 Utilization factor (%) M3 30 0 10 20 30 40 50 20 Chen M4 10 0 Via fill rate (%) Model validation (cont.) • Predictions for future designs • number of layers >>, die size < : f >>> • via impact severely underestimated • predicted limits on number of layers too high ISPD 2000, San Diego

  16. Model validation (cont.) • Predictions for future designs Number of terminal vias ISPD 2000, San Diego

  17. Outline • Models of achievable routing • Review of existing models • Validation of models through experiments! • Experimental analysis of assumptions • Future model requirements • Conclusions ISPD 2000, San Diego

  18. 80 70 60 50 Utilization factor (%) Chong 40 M3 30 20 Chen M4 10 0 Via fill rate (%) 0 10 20 30 40 50 Routing efficiency • Constant over all layers? ISPD 2000, San Diego

  19. Routing efficiency • Are we measuring routing efficiency or inefficiency? • thought experiment • given placement of given netlist • route with very good router, measure Ui • route again with very bad router, measure Ui • which one has better routing efficiency? • which one has higher utilization factor? • Give credit for completing nets, not for using metal (use Steiner length instead of actual length for Ui)! ISPD 2000, San Diego

  20. Layer assignment assumptions • shorter wires on lower tiers / wires on 1 tier Actual Length (%) Actual Number of Layers Steiner Length (m) Steiner Length (m) ISPD 2000, San Diego

  21. Real Wiring Effects • Cascade/ripple effect • Effect of vias depends on wire length • Proposal: l+1 intersections ISPD 2000, San Diego

  22. 80 70 60 50 Chong 40 Utilization factor (%) M3 30 20 Chen M4 10 Model M4 Model M3 0 0 10 20 30 40 50 Via fill rate (%) Real Wiring Effects (cont.) • A simple proposal • probability wire is not blocked: • via impact factor: ISPD 2000, San Diego

  23. Conclusion • Better/more accurate models needed • understanding routing efficiency • layer assignment model allows >1 tier/wire • via impact based on real wiring effects • wirelength on layer is important • cascade/ripple effect • Experimental verification of models a must! • There is a lot of work yet to be done ISPD 2000, San Diego

  24. Constant via impact factor • Utilization factor constant? M3/M4 Utilization factor ratio Via fill rate (%) ISPD 2000, San Diego

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