High Level Design using SyncCharts: a Case Study

1. Requirement 1 Requirement 2 Parity Violation Requirement 1: Requirement 2: Encoder/Decoder: Beyond the sixth instant: Bout is identical to Bin, upto a 6 instant delay Observer: a syncChart with preemption Observer: a flat syncChart = a FSM Observer: High Level Design using SyncCharts: a Case Study Charles André – I3S Lab. – Nice-Sophia Antipolis University/CNRS http://www.i3s.unice.fr SyncCharts Tools • A state-transition based model with • Hierarchy • Concurrent evolutions • Preemptions • A mathematical semantics • Synchronous process algebra • Fully compatible with the Esterel language • Can use mixed description • Graphical: SyncCharts • Textual: Esterel • Graphical Editor • Compiler SyncCharts  Esterel • Simulation • Xes (interactive esterel simulator • with source code debugging • Formal verification • Xeve (symbolic model-checker) Encoder/Decoder 0+-00-0+0 decoding encoding encoding:{0,1} *  {-U, 0, +U} * decoding:{-U, 0, +U} *  {0,1} * Standard encoding: In what follows: -U n; 0 z; +U p 0  z 1  {n,p} alternately 4 successive 0: 0 0 0 0  P z z V Example: design of the encoder Simulation SyncCharts-based Design • Decompose into interacting agents • Detector (4 consecutive 0’s) • Parity manager • Sequence generator • Output manager • Tests of scenarios (Esterel studio) • Prove safety properties • Circuit optimization (if HW controller) behavior Performance High-level behavioral description (e.g., the Encoder) a syncChart structural translation Esterel program Esterel’s compiler Blif 105 states SIS an optimized circuit 35 states As efficient as the hand-coded solution Safety Properties • Property: • At each instant : one and only one • signal in {n,z,p} is emitted • Observer: An Esterel module • loop • present (n and not z and not p) • or (not n and z and not p) • or (not n and not z and p) • else • emit non_exclusive • end present • each tick I3S Laboratory (UMR6070) BP121 – 06903 Sophia Antipolis cédex - FRANCE