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ENGG 1015 Tutorial

ENGG 1015 Tutorial. Three Examples of Finite State Machines Supplementary notes Learning Objective s Learn about Design of Finite State Machines Ack.: ISU CprE 281x, PSU CMPEN270, UPRM. To Detect if # of 1’s in Input is Divisible by 3.

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ENGG 1015 Tutorial

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  1. ENGG 1015 Tutorial • Three Examples of Finite State Machines • Supplementary notes • Learning Objectives • Learn about Design of Finite State Machines • Ack.: ISU CprE 281x, PSU CMPEN270, UPRM

  2. To Detect if # of 1’s in Input is Divisible by 3 • Design a state machine with 1 bit of input and 1 bit of output • The output bit will be 1 whenever the number of bits in input sequence is divisible by 3 • How many states do we need? • In state S0 (00), remainder = 0 (i.e., divisible by 3) • In state S1 ( 01), remainder = 1 • In state S2 (10), remainder = 2 • Output is 1 whenever in state S0

  3. Display Control • Design a state machine to display the characters in the string HELLO using a seven segment display • Five states in the FSM • In state S0 (000) we display H • In state S1 (001) we display E • In state S2 (010) we display L • In state S3 (011) we display L • In state S4 (100) we display O • State transitions are S0  S1, S1  S2, S2  S3,S3  S4, S4  S0

  4. Display Control

  5. Digital Combination Lock • Three bit serial lock controls entry to locked room • Locks generates an UNLOCK signal when key matches internal combination. ERROR light illuminated if key does not match combination. • Inputs: RESET, ENTER, 2 position switch for bit of key data. • Sequence • Press RESET • Enter key bit • Press ENTER • Repeat (2) & (3) two more times.

  6. Digital Combination Lock • Problem specification is incomplete • How do you set the internal combination? • Exactly when is the ERROR light asserted? • Make reasonable assumptions • Assert as soon as error is detected vs. wait until full combination has been entered • Our design • Registered combination plus error after full combination

  7. Digital Combination Lock • After understanding the problem, we draw a block diagram • Inputs: Reset, Enter, Key-In, L0, L1, L2 • Outputs: Unlock, Error • Then derive thestate transitiondiagram

  8. Digital CombinationLock • Abstractions in machine design • Based on the requirement,we design the FSM • Based on the FSM, we computetruth table, and then deriveBoolean expressions for statetransition logic and output logic • Based on Boolean expressions,we design circuits • Based on the designed circuit, weimplement the circuit on FPGA.

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