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Powering Interlocks

Powering Interlocks. Markus Zerlauth AB/CO/MI. Power converters, magnet protection and powering interlocks. Arc cryostat. DFBAO. Amalia/Luigi. Karl-Hubert. Quench Detector. Quench Detector. Quench Heater PS. Quench Detector. Quench Heater PS. Energy Extraction. Reiner.

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Powering Interlocks

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  1. Powering Interlocks Markus Zerlauth AB/CO/MI

  2. Power converters, magnet protection and powering interlocks Arc cryostat DFBAO Amalia/Luigi Karl-Hubert Quench Detector Quench Detector Quench Heater PS Quench Detector Quench Heater PS Energy Extraction Reiner Power Converter David QPS Controller Tunnel Cryo OK Powering Interlocks Thomas UPS / AUG OK QPS  OK UA83 Rudiger Permit Powering

  3. Outline • Why do we use Powering Interlock Systems for the LHC? • Main functionalities of the system in the LHC powering • Hardware Architecture and Hardwired interlock loops • What is an interlock type A, B1, B2 and C? • Links with other systems, AUG / UPS, cryogenics • Constraints on operation and commissioning and Startup interlocks • Supervision application

  4. Main functionalities & requirements • Powering Interlock Controllers (PIC) assure that all conditions for safe magnet powering are met • Upon Start-up • During operation • Protection on a circuit by circuit basis • Additional protection mechanisms on a powering subsector basis • Linking magnet powering to technical services & safety systems (UPS, AUG, Cryogenics) • Linking magnet powering to beam interlock system • Provide the evidence of powering failures to the operator

  5. Conditions for powering Cryogenics: Magnetandcurrent leadsmust be at correct temperature Safety systems: must be ready (AUG – arret urgence general, UPS – uninterruptible power supplies, …) Power converter: must be ready (including cooling water etc.) Quench protection system: must be ready (quench heaters charged, extraction switch closed) Power converters Operator / Controls: must give permission to power Powering Interlock Controller (PIC) Energy extraction Warming up of the magnet due to failure in the cryogenic system Warming up of the magnet due to quench in an adjacent magnet AUG or UPS fault Power converterfailure Quenchin a magnet inside the electrical circuit

  6. Powering Interlocks – the circuit level PIC DFB Magnet • All conditions met for powering: PC_PERMIT • Sum of internal converter faults: POWERING_FAILURE • Magnet quench or Fast Abort from PIC: PC_FAST_ABORT • Loss of coolant: PC_DISCHARGE_REQUEST Cryostat Magnet Magnet … PC_PERMIT QPS PC PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_DISCHARGE_REQUEST DISCHARGE_REQUEST • No direct connection Magnet Protection – Converters (as e.g. in SPS), but use of industrial controllers (PLCs) • Protection signals are exchanged via hardwired current loops • Depending on stored energy, circuit complexity, QPS, etc.. in between 2-4 signals are exchanged / circuit Naming DB for official signal names

  7. Interlock Types PC_PERMIT QPS PIC PC Interlock Type A (=13kA main + IT) PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_DISCHARGE_REQUEST DISCHARGE_REQUEST PC_PERMIT_B1 PC PC_PERMIT_B2 QPS PIC PC Interlock Type B2 (=all quads of IPQD) PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT QPS PIC PC Interlock Type B1 (=600A EE, 600A no EE, 600A no EE crowbar + all dipoles of IPQD) PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_PERMIT PIC PC Interlock Type C (= 80-120A) POWERING_FAILURE

  8. Hardwired signals - Power Permit Loop +15 ,,, 24 V Cable PIC-PC Powering Permit: CMD_PWR_PERM_PIC Switch closed: permission for powering Switch open: no permission for powering ST_UNLATCHED:PWR_PERMIT Signal present: Powering permitted Signal to FALSE: Powering not permitted (latched) GND Power Converter Powering Interlock Controller by R.Schmidt LHC-D-ES-0003-10-02

  9. Hardwired signals – Circuit Quench Loop Circuit Quench ST_CIRCUIT_OK_QPS Switch closed: no quench Switch open: quench +15 ,,, 24 V Quench detection Energy extraction 600 A Signal present: no Fast Power Abort ST_ABORT_PIC Signal not present: Fast Power Abort ST_FAST_POWER_ABORT Signal present: no Fast Power Abort Signal to FALSE: Fast Power Abort ST_FAULTS:FAST_ABORT Signal present: no Fast Power Abort Signal to FALSE: Fast Power Abort (latched) PIC Fast Power Abort Request CMD_ABORT_PIC Switch closed: operation ok Switch open: Fast Power Abort GND Powering Interlock Controller Power Converter

  10. Physical installations in RR77 Powering Interlock System QPS 600A protection unit 600A EE system 600A converter

  11. Physical installations in RR77 Patch Panels Industrial Controller

  12. Cryostats and interlock systems in sector 7-8 3 powering subsectors - XL8 (DFBXG) - ML8 (DFBMA,DFBMC) - A78 (DFBAO-DFBAN- DFBMH) CIP.XL8 CIP.ML8 CIP.AL8 CIP.AR7 Point 7 (Ferney) Point 8 (Leclerc) A78 ML8 XL8 view from outside LHC ring

  13. Architecture • 28 powering subsectors • 36 interlock controllers (2 for long arcs) • 5-43 circuits / controller

  14. Powering Interlocks – ‘global’ interlocks DFB Magnet CRYO_MAINTAIN • PLC-PLC connection in between interlocks and cryogenics • 1 signal / powering subsector • Creates a slow power abort in ALL circuits of the subsector Cryostat Magnet Magnet … PC QPS PC QPS PC_PERMIT QPS 1 PIC PC PC_FAST_ABORT CIRCUIT_QUENCH x M x N POWERING_FAILURE PC_DISCHARGE_REQUEST DISCHARGE_REQUEST Global interlocks • In addition to circuit/circuit treatment, global interlocks will provoke runtime aborts of ALL circuits in a subsector • Exchanged via hardware or between PLC-PLC

  15. Powering Interlocks – ‘global’ interlocks AUG_OK • Hardwired interlock, connecting all AUG chains of an LHC point • 1 signal / LHC point, seen by all powering subsectors • Creates a fast power abort in ALL circuits of the subsectors UPS_OK • Hardwired interlock, connecting all redundant UPS systems of an LHC point + related alcoves • 1 signal / LHC point, seen by all powering subsectors • Creates a fast power abort in ALL circuits of the subsectors Quench Propagation • From String 2 experience -> Anticipate circuit aborts to avoid additional quenches in adjacent magnets • 1 signal / powering subsector • Creates a fast power abort in ALL circuits of the subsectors

  16. Powering Interlocks – start-up interlocks QPS_OK • Start-up interlock, exchanged in between PVSS applications • 1 signal / circuit, assuring full redundancy and operation of related QPS equipment • If lost during powering, no abort QPS_OK QPS SCADA PIC SCADA Surface – ‘Software’ signal exchange Tunnel – Hardwired signal exchange PC_PERMIT QPS PIC PC PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_DISCHARGE_REQUEST DISCHARGE_REQUEST Start-up interlocks • In addition to hardwired interlocks, several software interlocks exist • Exchanged via CMW, DIP, etc between SCADA systems • Verified ONLY upon start-up, thus not provoking aborts during powering

  17. Powering Interlocks – start-up interlocks CRYO_START • Start-up interlock, exchanged in between PVSS applications • 1 signal / subsector, assuring cryogenic conditions of subsector before start-up • If lost during powering, no abort CRYO_START CRYO SCADA QPS SCADA PIC SCADA Surface – ‘Software’ signal exchange Tunnel – Hardwired signal exchange PC_PERMIT QPS PIC PC PC_FAST_ABORT CIRCUIT_QUENCH POWERING_FAILURE PC_DISCHARGE_REQUEST DISCHARGE_REQUEST

  18. Powering Interlocks – start-up interlocks UPS_START • Start-up interlock, exchanged in between SCADA applications • 1 signal / subsector, assuring full redundancy of UPS systems CABLE_CONNECT • Start-up interlock, verification that all required cables are connected to interlock system • 1 signal / cable CONFIG_DATA • Start-up interlock, verification that all configuration data of an interlock system is consistent • 1 flag / system

  19. Constraints on circuit powering – Use Case Type A Type B2 Type B1 Type C

  20. Constraints on circuit powering – Use Case Typical Sequence • Verify no Global interlock is pending • Close EE systems (if existing) and re-arm QPS system via QPS supervision • Unlatch Interlocks (SIGNAL Init) • Clear PC faults (equipment stop, OFF to converter) • -> Circuit ready for powering 1. Type B1 3.

  21. Constraints on circuit powering – Use Case Typical Sequence • Verify no Start-up interlock is pending • If circuit ‘ready to permit’ • Give Permit 6. 6. 7. 8.

  22. PVSS Expert screens & History Buffer

  23. Conclusions • Powering Interlock system along with its clients assures all conditions for safe powering are met at any time • Safety critical protection on a circuit / circuit level via hardwired interlocks • Additional software interlocks for start-up • During commissioning ONLY, some of these start-up interlocks can be masked by the expert • After interlock commissioning (PIC1 and PIC2, see later presentations), system is considered operational • No modifications or tampering with interlocks after this phase

  24. Questions?

  25. Glossary • Powering Interlocks • Powering Interlock Controller • Programmable Logic Controller (PLC) • Powering Subsector • PVSS supervision • Interlock Types • Hardwired interlocks • Global Protection mechanism • Quench Propagation • Current Loops • AUG, UPS, Cryogenics, QPS • Startup Interlocks • Runtime Interlocks

  26. Documentation Specification for HW Interfaces of the PIC: EDMS DocNr.:LHC-D-ES-0003 Hardware Interfaces with UPS/AUG: EDMS DocNr.:LHC-CIP-ES-0001 General procedure for HW commissioning: EDMS DocNr.:LHC-D-HCP-0001 Specification for Interlock commissioning procedures: EDMS DocNr.:LHC-D-HCP-0002 Procedures for automated commissioning: EDMS DocNr.:LHC-D-HCP-0005 Powering Subsectors in the LHC: EDMS DocNr.:LHC-D-ES-0002 PIC configuration files: http://cs-ccr-oas2/PIC/listpicnames.do PIC layout configuration + Electrical Circuits: http://layout.web.cern.ch/layout/

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