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Integrated Circuit Design Lecture 8 (this lecture adopted from © 2002 Prentice Hall)

Integrated Circuit Design Lecture 8 (this lecture adopted from © 2002 Prentice Hall). Seungjun Lee Information Electronics Eng. Ewha Womans University. Review. So far, we have reviewed Device characteristics (Ch. 3) Diode and MOS transistor Inverter Basics (Ch. 1) CMOS Inverter (Ch. 5)

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Integrated Circuit Design Lecture 8 (this lecture adopted from © 2002 Prentice Hall)

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  1. Integrated Circuit DesignLecture 8(this lecture adopted from © 2002 Prentice Hall) Seungjun Lee Information Electronics Eng. Ewha Womans University

  2. Review • So far, we have reviewed • Device characteristics (Ch. 3) • Diode and MOS transistor • Inverter Basics (Ch. 1) • CMOS Inverter (Ch. 5) • Voltage Transfer Characteristic • Propagation Delay • Power Consumption • Impact of Technology Scaling

  3. In This Lecture • Combinational Logic Design • Static CMOS design • Complementary CMOS • Ratioed Logic • Pass-Transistor Logic

  4. Combinational vs. Sequential Logic

  5. Static CMOS Circuit • At every point in time (except during the switching transients) each gate output is connected to either VDD or GND via a low-resistive path. • The outputs of the gates assume the value of the Boolean function at all times (ignoring, once again, the transient effects during switching periods). • This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance

  6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  7. PMOS Transistors in Series/Parallel Connection

  8. CL CL CL CL Threshold Drops VDD VDD S D VDD D S 0 VDD 0 VDD - VTn VGS VDD 0 VDD |VTp| VGS D S VDD S D

  9. Construction of Complementary CMOS Logic VDD B A Out Out A B

  10. Construction of Complementary CMOS Logic VDD B A Out A B Out = AB

  11. Complementary CMOS Logic PUN: Pull-Up Network Out PDN: Pull-Down Network PUN and PDN are Dual Network Complementary CMOS gates are ‘inverting’

  12. Example Gate: NAND

  13. Example Gate: NOR

  14. Example Gate: COMPLEX CMOS GATE Out =

  15. Constructing a Complex Gate

  16. Constructing a Complex Gate • Out = (AB + C)D

  17. Properties of Complementary CMOS Gates

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