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Floorplanning Pipelined Arrays Using Sequence Pairs for Efficient Design Synthesis

This document outlines the methodology for floorplanning pipelined arrays (FoPA) with a focus on sequence pairs to enhance design efficiency. It discusses previous works on sequence pairs, introduces new additions, and presents results in the context of cryptography, signal processing, and future microprocessor memory systems. Key aspects include maintaining module structure during physical design, addressing wire congestion issues, and utilizing various floorplanning tools. The new approaches aim to create better placement outcomes, leading to smaller, faster designs after placement and routing.

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Floorplanning Pipelined Arrays Using Sequence Pairs for Efficient Design Synthesis

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  1. Floorplanning of Pipelined Array (FoPA) Modules using Sequence Pairs Matt Moe Herman Schmit

  2. Outline • Pipelined Arrays • Previous Sequence Pair work • Sequence Pair additions • Results

  3. Cryptography Control Signal Processing Microprocessor Memory System of the Future • Soft IP cores • hardware accelerators • pipelined arrays

  4. Logic Logic Logic Pipelined Arrays Logic • Systolic architecture • Easy to compile to • Fast throughput aftersynthesis • Structure lost duringphysical design pipeline stage Logic array adjacent pipelinestages Logic

  5. Logic Logic Logic Physical Design of Pipelined Arrays • Maintain structure • One pipeline stage =one floorplan module • Use floorplanning tools to create placement constraints floorplan module array adjacent modules

  6. How do you maintain the structure? • If modules were the same size - trivial solutions 1 1 9 1 8 9 2 3 2 8 2 7 6 4 3 7 5 6 4 6 3 4 5 7 8 9 5

  7. More interesting problem… • Modules vary in size • Wire Congestion • Created by non-adjacencyof modules • Forces extra areausage 0 8 11 7 10 9 1 6 5 2 3 4

  8. Classic Simulated Annealing of Sequence Pairs • Sequence Pair • Floorplan representation that describes directional constraints between every possible pair of blocks • Large design space • H. Murata, et.al., “VLSI Module Placement Based on Rectangle Packing by the Sequence Pair,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1518-1524, December 1996.

  9. A B C D A D C B Classic Swap Move B A A B C C D A D C B A B C D D A C B D A CB D

  10. A B C D ABCD DACB Oblique Constraint Graph Oblique Connnectivity Graph B B A A C C A B C D A B C D D A C B D A C B D D

  11. A B C D B A C A B C D D A C B D FoPA Delete / Insert Move A C B A B C D D B AC D A C B D

  12. A B C D B A C A B C D D A C B D Restricted Delete / Insert Move C B A A C B D D A C B D A C B D

  13. This looks better… • All logically array adjacent elements are adjacent in thefloorplan • Reduced wirecongestion 9 8 7 10 11 6 3 4 5 2 1 0

  14. Floorplanning Results • Block sizes created from fastest synthesized designs • Each point represents the best score from 10 annealing runs

  15. Floorplan Utilization

  16. Longest Wire Length

  17. Results afterPlacement and Routing • Floorplans used as constraints in Monterey Design System’s Dolphin • Iteratively expand floorplans by 1% until routable • Delay reported by Dolphin

  18. Added Area

  19. Added Delay

  20. Average Placed and Routed Results

  21. Conclusions • New restricted move set • Creates better placement of modules during floorplanning synthesis • Creates smaller and faster designs after placement and routing • In paper • New wire length model • Cost Metric

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