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Opportunities for Gigascale Integration in Three Dimensional Architectures

Opportunities for Gigascale Integration in Three Dimensional Architectures. James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics Research Center Georgia Institute of Technology SLIP Workshop 2000 9 April 2000 Supported by DARPA and SRC. Outline. Motivation

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Opportunities for Gigascale Integration in Three Dimensional Architectures

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  1. Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics Research Center Georgia Institute of Technology SLIP Workshop 2000 9 April 2000 Supported by DARPA and SRC

  2. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  3. Motivation • 10% of Interconnects = 80% of Wire Length. • KEEP INTERCONNECTS SHORT!!

  4. Motivation • Each gate has more neighboring gates. 2D 3D

  5. Motivation • Reduction of gate pitch due to smaller wire-limited area. 2D 3D

  6. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  7. 3D Architecture Concepts • Stratum - A layer of transistors with its tiers of interconnects. • Tier - A pair of orthogonal metal levels with equal pitch. Tier 2 Stratum 1 Tier 1 Tier 2 Stratum 2 Tier 1

  8. 3D Architecture Concepts • Stratal- to gate- pitch ratior. Stratum 1 Stratum 2

  9. 3D Architecture Concepts Importance of r • Height of metal stack is at least as great as the gate pitch (r > 1). • Substrate thickness for mechanical stability. • Thermal/electrical insulation of strata. • r affects the probability of running an interconnect vertically.

  10. 3D Architecture Concepts • Gate pair – two gates separated by a given manhattan length. • Length in manhattan geometry.

  11. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  12. Derivation of 3D Model • Need two values. • Number of expected interconnects between a gate pair (probability of occupation). • Use Rent’s Rule. • Number of gate pairs (density of states). • Use discrete convolution.

  13. Derivation of 3D Model Number of Expected Interconnects • Expression from Rent’s Rule. 2D B A B C 1D C B B C B C B C A B B C C

  14. Derivation of 3D Model • Manhattan sphere instead of circles. 3 3 2 3 3 2 1 2 3 4 4 3 2 3 4 4 3 4 4

  15. Derivation of 3D Model • Edge effects. Horizontal 3 3 2 3 3 2 1 2 3 4 4 3 2 3 4 4 3 4 4

  16. Derivation of 3D Model 3 3 3 3 3 2 2 1 2 2 • Edge effects. Vertical 3 3 3 3 3 4 4 3 3 4 4 3 4 4

  17. Derivation of 3D Model • Use of averaging to avoid both horizontal and vertical edge effects. • A function for the number of starting gates must be defined. Number of Gate Pairs Number of Starting Gates

  18. Derivation of 3D Model • Starting gate – a gate that can serve as the NA of a gate pair for a given length. X X X X X 1D X Length = 5 2D X X X X X X X X X

  19. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  20. Comparison with 2D

  21. Variable r

  22. Variable Strata

  23. Wire Demand

  24. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  25. Optimization Interconnect Distribution Area Required Dn Delay Equation Ln-1 Ln • Solve equations simultaneously. • pn is pitch required such that wire length Ln meets delay. • Ln is limited by the available area for a tier and the pitch.

  26. Optimization 950 MHz Wire-Limited Area Metal Levels • 50% reduction in metal levels • 39% reduction in area • 92% reduction in area

  27. Optimization Wire-Limited Clock Frequency • 14x increase in clock frequency • 63% reduction in area

  28. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  29. Limitations Vertical Wiring Density Pad - Stratum 1 Alignment Tolerance Cross-section Pad - Stratum 2 • Vertical interconnect pitch must be greater than alignment tolerance. • Demonstrated alignment tolerance : 3 microns.

  30. Limitations • Restrictions placed by density of vertical interconnects may require increased area. • For frequency optimization, required alignment tolerance is 0.34 microns. • Via aspect ratio may also add limitations on vertical wiring density.

  31. Outline • Motivation • 3D Architecture Concepts • Derivation of 3D Model • Results of Model • Optimization of Interconnects • Wiring Density Limitations • Conclusions

  32. Conclusions • A new model has been derived for interconnect distributions in 2D and 3D architectures. • 14x increase in wire-limited clock frequency, • 92% reduction in wire-limited area, • or 50 % reduction in metal levels for 3D system. • Restrictions on vertical interconnect density may compromise the advantages of 3D architectures.

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