1 / 39

Gates – Part 1

Gates – Part 1. Gates are Built With Transistors. drain. drain. drain. no current flows. 3 volts. 0 volts. gate. current flows. source. source. source. nFET. nFET On. nFET Off. N-type field-effect transistor = nFet. Gates are Built With Transistors. source. source. source.

aminia
Télécharger la présentation

Gates – Part 1

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Gates – Part 1 ECEn 224

  2. Gates are Built With Transistors drain drain drain nocurrentflows 3 volts 0 volts gate currentflows source source source nFET nFET On nFET Off N-type field-effect transistor = nFet ECEn 224

  3. Gates are Built With Transistors source source source nocurrentflows 0 volts 3 volts gate currentflows drain drain drain pFET pFET On pFET Off P-type field-effect transistor = pFet ECEn 224

  4. x x’ Complement Also known as invert or not. This is a schematic symbol. It is a graphical representationof a circuit which implementsthe operation. ECEn 224

  5. FET-Based Inverter Vcc = 3V Vcc = 3V Vcc = 3V off on Vin Vout 3V 0V 0V 3V on off GND = 0V GND = 0V GND = 0V “Ground” ECEn 224

  6. A Q A B Q B AND and OR Gates ECEn 224

  7. Boolean Expressions and Gates Each Boolean expression has a corresponding realization with logic gates. F = A’ + B C A F B C ECEn 224

  8. NAND Gates AND NAND A Q B Q is true iff A AND B are true Bubble means NOT NAND A Q A B Q B Q is false iff A AND B are true ECEn 224

  9. Vcc Vcc GND GND FET-Based NAND Gate Vcc A B 1 1 1 0 off off off on F 0 1 A 1 1 on on B 1 0 on off GND ECEn 224

  10. NOR Gates OR NOR A Q B Q is true if A OR B is true NOR A Q B A Q B Q is false if A OR B is true ECEn 224

  11. A B F A B FET-Based NOR Gate Vcc = 5V Can you complete the truth table? GND ECEn 224

  12. A B F A B FET-Based NOR Gate Vcc = 5V Can you complete the truth table? GND ECEn 224

  13. FET-Based Gates • P-type FETs must be on top of gate • N-type FETs must be on bottom of gate • Due to electrical characteristics of the two FET types • Output is driven to either ‘1’ or ‘0’ • never both • never neither ECEn 224

  14. Exclusive-OR (XOR) Output is true iff inputs are different. A Q = A  B = A’B + AB’ B Another definition: Q is true iff A does not equal B ECEn 224

  15. Exclusive-OR Theorems The first 4 are important, the others are used less frequently ECEn 224

  16. Equivalence Operation  denotes equivalence (also written as X==Y) Output is true iff inputs are equal X Q = (X==Y) = X’Y’ + XY  Y ECEn 224

  17. XOR and EQUIV are Complements !! Alternate equivalence symbol Gate often called exclusive NORor XNOR ECEn 224

  18. Vcc Vcc A B C A B F F A A B B C GND GND Multi-Input Gates   Which one will be slower/faster? ECEn 224

  19. Alternative Gate Symbols The symbolic meaning of the circuit should be clear from what you draw... ECEn 224

  20. Alternative Gate Symbols A A Q Q B B Q is true iff A is false OR B is false A Q A B Q B Q is true iff A is false AND B is false ECEn 224

  21. Alternative Gate Symbols • Turn on sprinklers if it is not a holiday and it is not a weekend or? The problem statement uses AND, so use the AND symbol ECEn 224

  22. Alternative Gate Symbols • Turn off the sprinklers if it is a holiday or it is a weekend or? The problem statement uses OR, so use the OR symbol ECEn 224

  23. Another Example • Design a circuit to determine whether the bits of a 4-bit wire are all zero This is the appropriate symbol to use… ECEn 224

  24. Mixed Symbols • Such a gate doesn’t likely exist • Build from AND gate and inverter • Simplifies schematics, enhances readability A Q B Q is true iff A is false AND B is true ECEn 224

  25. Single Gate Conversion Rules • How to change one symbol to another: • Change symbol • AND to OR • OR to AND • Invert all inputs and outputs • No change in behavior – merely a symbol change A A Q Q B B Q is true iff A is false AND B is true Q is false if A is true OR B is false ECEn 224

  26. Alternative Gate Symbols - Summary • Use the symbol that matches the problem statement • Clarity • Documentation • Maintenance • If function is correct but symbol is wrong then your schematic is wrong ECEn 224

  27. Positive vs. Negative Logic ECEn 224

  28. Positive Logic and Negative Logic V1 Logic Gate V2 Vout V3 ECEn 224

  29. Positive Logic Let: 0 volts => 0 5 volts => 1 The circuit is a logical AND gate ECEn 224

  30. Negative Logic Let: 0 volts => 1 5 volts => 0 The same circuit is a logical OR gate ECEn 224

  31. Positive/Negative Logic • The most common mapping is positive logic:+V  1 0V  0 • Different systems have used different mappings in the past ECEn 224

  32. Multi-Level Logic ECEn 224

  33. Levels of a Network Maximum number of gates between an input and the output 5 Levels • In general: • - the more levels, the slower the circuit 3 Levels ECEn 224

  34. Number of Levels • Number of levels can be increased by factoring • Number of levels can be decreased by multiplying out • Changing the number of levels affects area and speed G = AB + ACDE + ACF = A(B+CDE+CF) G = A(B+CDE+CF) = AB + ACDE + ACF ECEn 224

  35. Example Levels = 2 Gates = 4 Delay = tAND4 + tOR3 Gate Inputs = 12Transistors = 24 Largest gate = 4 inputs G = AB + ACDE + ACF A B Area Calculations: - Each input to a gate costs ~2 transistors - Area  number of transistors Delay Calculations: - Find slowest path from inputs to output tdelay = tAND4 + tOR3 - The 4-input AND is likely slower than the other AND gates A C G D E A C F ECEn 224

  36. factor C D E C G F A B Change the number of levels by factoring G = ACDE + ACF + AB = A(CDE + CF + B) Levels = 3 Gates = 4 Delay = tAND3 + tOR3 + tAND2 Inputs = 10Transistors = 20 Largest gate = 3 inputs This is a 3-level circuit… ECEn 224

  37. factor A G B D C E F Factor Again G = A(CDE + CF + B) = A[B+C(F+DE)] Levels = 5 Gates = 5 Delay = 3 x tAND2 + 2 x tOR2 Inputs = 10Transistors = 20 Largest gate = 2 inputs This is a 5-level circuit… ECEn 224

  38. Changing the number of levels Three alternative solutions for same function… Each has different area/speed characteristics ECEn 224

  39. Two-Level vs. Multi-Level • In general: • Two-level is fastest • Multi-level can be smaller • Exploring by hand to find just the right solution can be difficult • We will focus on two-level • Easy to get from truth table • Minimization techniques in later chapters focus on it ECEn 224

More Related