Download
slide1 n.
Skip this Video
Loading SlideShow in 5 Seconds..
Figure 7.1 Control of an alarm system PowerPoint Presentation
Download Presentation
Figure 7.1 Control of an alarm system

Figure 7.1 Control of an alarm system

151 Views Download Presentation
Download Presentation

Figure 7.1 Control of an alarm system

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Set Sensor ¤ On Off Memory Alarm element Reset Figure 7.1 Control of an alarm system

  2. A B Figure 7.2 A simple memory element

  3. Load A B Output Data TG1 TG2 Figure 7.3 A controlled memory element

  4. Reset Set Q Figure 7.4 A memory element with NOR gates

  5. Q S R Q R a b Q a (no change) 0 0 0/11/0 0 1 0 1 1 0 1 0 1 1 0 0 Q b S (a) Circuit (b) Truth table t t t t t t t t t t 1 2 3 4 5 6 7 8 9 10 1 R 0 1 S 0 1 Q ? a 0 1 Q ? b 0 Time (c) Timing diagram Figure 7.5 A latch built with NOR gates

  6. ( ) Q t + 1 Clk S R ¢ R R Q 0 x x Q( t ) (no change) 1 0 0 Q( t ) (no change) Clk 1 0 1 0 1 1 0 1 Q 1 1 1 x Q S S ¢ S Clk (a) Circuit (b) Truth table R Q 1 Clk (d) Graphical symbol 0 1 R 0 1 S 0 1 ? Q 0 1 ? Q 0 Time (c) Timing diagram Figure 7.6 Gated SR latch

  7. S Q Clk Q R Figure 7.7 Gated SR latch with NAND gates

  8. ( ) Clk D Q t + 1 S ( ) Q t 0 x D 1 0 0 (Data) Q 1 1 1 (b) Truth table Clk Q Q D R (a) Circuit Clk Q t t t t (c) Graphical symbol 1 2 3 4 Clk D Q Time (d) Timing diagram Figure 7.8 Gated D latch

  9. t su t h Clk D Q Figure 7.9 Setup and hold times

  10. Master Slave Q Q m s Q Q D D Q D Clk Clk Clock Q Q Q (a) Circuit Clock D Q m Q D Q = Q s Q (b) Timing diagram (c) Graphical symbol Figure 7.10 Master-slave D flip-flop

  11. Q D Clock Q (b) Graphical symbol 1 P3 P1 2 5 Q Clock 6 Q P2 3 4 P4 D (a) Circuit Figure 7.11 A positive-edge-triggered D flip-flop

  12. Q D D Q a Clock Q Q Clk a Q D Q b (b) Timing diagram Q Q b Clock (a) Circuit Q Q D D c Q Q Q c a Q b Q c Figure 7.12 Comparison of level-sensitive and edge-triggered

  13. Preset D Q Clock Q Clear (a) Circuit Preset Q D Q Clear (b) Graphical symbol Figure 7.13 Master-slave D flip-flop with Clear and Preset

  14. Preset Q Clock Preset Q Q D Q D Clear Clear (b) Graphical symbol (a) Circuit Figure 7.14 Positive-edge-triggered D flip-flop with Clear and Preset

  15. Figure 7.15 Synchronous reset for a D flip-flop

  16. Q T Q Q D Q (c) Graphical symbol T Q Q ( ) Q t + 1 T ( ) 0 Q t Clock ( ) 1 Q t (a) Circuit (b) Truth table Clock T Q (d) Timing diagram Figure 7.16 T flip-flop

  17. J Q D Q K Q Q Clock (a) Circuit Q ( t + 1 ) J K 0 0 Q ( t ) J Q 0 1 0 1 0 1 K Q 1 1 Q ( t ) (b) Truth table (c) Graphical symbol Figure 7.17 JK flip-flop

  18. Q Q Q Q 1 2 3 4 In Out Q Q Q Q D D D D Clock Q Q Q Q (a) Circuit Q Q Q Q = Out In 1 2 3 4 t 1 0 0 0 0 0 t 0 1 0 0 0 1 t 1 0 1 0 0 2 t 1 1 0 1 0 3 t 1 1 1 0 1 4 t 0 1 1 1 0 5 t 0 0 1 1 1 6 t 0 0 0 1 1 7 (b) A sample sequence Figure 7.18 A simple shift register

  19. Parallel output Q Q Q Q 3 2 1 0 Q Q Q Q D D D D Q Q Q Q Serial Clock Shift/Load input Parallel input Figure 7.19 A simple shift register

  20. 1 Q Q Q T T T Clock Q Q Q Q Q Q 0 1 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 6 7 0 (b) Timing diagram Figure 7.20 A three-bit up-counter

  21. 1 Q Q Q T T T Clock Q Q Q Q Q Q 0 1 2 (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 7 6 5 4 3 2 1 0 (b) Timing diagram Figure 7.21 A three-bit down-counter

  22. Clock cycle Q Q Q 2 1 0 Q changes 1 0 0 0 0 Q changes 2 1 0 0 1 2 0 1 0 3 0 1 1 4 0 0 1 5 1 0 1 6 1 0 1 7 1 1 1 8 0 0 0 Table 7.1 Derivation of the synchronous up-counter

  23. 1 Q Q Q Q T T T T Q Q Q Q 0 1 2 3 Clock Q Q Q Q (a) Circuit Clock Q 0 Q 1 Q 2 Q 3 Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 (b) Timing diagram Figure 7.22 A four-bit synchronous up-counter

  24. Enable Q Q Q Q T T T T Clock Q Q Q Q Clear Figure 7.23 Inclusion of enable and clear capability

  25. Enable 1 D Q 0 0 0 D Q 0 1 1 D Q 0 2 2 Load Clock Clock (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 (b) Timing diagram Figure 7.26 A modulo-6 counter with synchronous reset

  26. 1 Q Q Q T T T Q Q Q 0 1 2 Clock Q Q Q (a) Circuit Clock Q 0 Q 1 Q 2 Count 0 1 2 3 4 5 0 1 2 (b) Timing diagram Figure 7.27 A modulo-6 counter with asynchronous reset

  27. Enable 1 D Q 0 0 0 D Q 0 1 1 BCD D Q 0 0 2 2 Q D 0 3 3 Load Clock Clock Enable Clear D Q 0 0 0 D Q 0 1 1 BCD 1 D Q 0 2 2 D Q 0 3 3 Load Clock Figure 7.28 A two-digit BCD counter

  28. Q Q Q 0 1 n – 1 Q Q Q D D D Q Q Q Reset Clock Figure 7.30 Johnson counter

  29. Figure 7.31 Three types of storage elements in a schematic

  30. Data Clock Latch Figure 7.32 Gated D latch generated by CAD tools

  31. Figure 7.34 Timing simulation of storage elements

  32. LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY altera ; USE altera.maxplus2.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Resetn, Presetn : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END flipflop ; ARCHITECTURE Structure OF flipflop IS BEGIN dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ; END Structure ; Figure 7.35 Instantiating a D flip-flop from a package

  33. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY implied IS PORT ( A, B : IN STD_LOGIC ; AeqB : OUT STD_LOGIC ) ; END implied ; ARCHITECTURE Behavior OF implied IS BEGIN PROCESS ( A, B ) BEGIN IF A = B THEN AeqB <= '1' ; END IF ; END PROCESS ; END Behavior ; Figure 7.36 Implied memory

  34. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clk : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ; ARCHITECTURE Behavior OF latch IS BEGIN PROCESS ( D, Clk ) BEGIN IF Clk = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.37 Code for a gated D latch

  35. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.38 Code for a D flip-flop

  36. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior ; Figure 7.39 Code for a D flip-flop using WAIT UNTIL

  37. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.40 D flip-flop with asynchronous reset

  38. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Resetn = '0' THEN Q <= '0' ; ELSE Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.41 D flip-flop with synchronous reset

  39. Figure 7.42 The lpm_ff parameterized flip-flop module

  40. Figure 7.43 An adder with registered feedback

  41. Figure 7.44 Timing simulation

  42. LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY lpm ; USE lpm.lpm_components.all ; ENTITY shift IS PORT ( Clock : IN STD_LOGIC ; Reset : IN STD_LOGIC ; Shiftin, Load : IN STD_LOGIC ; R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift ; ARCHITECTURE Structure OF shift IS BEGIN instance: lpm_shiftreg GENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => "RIGHT") PORT MAP (data => R, clock => Clock, aclr => Reset, load => Load, shiftin => Shiftin, q => Q ) ; END Structure ; Figure 7.45 Instantiation of the lpm_shiftreg module

  43. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg8 IS PORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; END reg8 ; ARCHITECTURE Behavior OF reg8 IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= "00000000" ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.46 Code for an eight-bit register with asynchronous clear

  44. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY regn IS GENERIC ( N : INTEGER := 16 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ; ARCHITECTURE Behavior OF regn IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= (OTHERS => '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.47 Code for an n-bit register with asynchronous clear

  45. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY muxdff IS PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ; END muxdff ; ARCHITECTURE Behavior OF muxdff IS BEGIN PROCESS BEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = '0' THEN Q <= D0 ; ELSE Q <= D1 ; END IF ; END PROCESS ; END Behavior ; Figure 7.48 Code for a D flip-flop with a 2-to-1 multiplexer on the D input