ABC: A System for Sequential Synthesis and Verification

ABC: A System for Sequential Synthesis and Verification Berkeley Logic Synthesis and Verification Group Robert Brayton Alan Mishchenko

Overview • Introduction • What and why ABC? • ABC fundamentals • Areas addressed by ABC • Synthesis • Technology mapping • Verification • Contrast with classical methods • How is ABC different from SIS? • Recent work • Speedup • Factoring • Don’t-care based optimization • Scalable sequential synthesis • WireMap • White boxes

A Plethora of ABCs http://en.wikipedia.org/wiki/Abc • ABC (American Broadcasting Company) • A television network… • ABC (Active Body Control) • ABC is designed to minimize body roll in corner, accelerating, and braking. The system uses 13 sensors which monitor body movement to supply the computer with information every 10 ms… • ABC (Abstract Base Class) • In C++, these are generic classes at the base of the inheritance tree; objects of such abstract classes cannot be created… • ABC (supposed to mean “as simple as ABC”) • A system for sequential synthesis and verification at Berkeley

BDD Why We Decided to Build ABC • SIS • Outdated, but many research papers on how a new algorithm beats SIS results • Not supported • MVSIS • Gave us a reason to work on logic synthesis • Learned a lot about new methods and better data structures • Could see how specializing to binary could provide substantial improvements. • ABC • Initial intention was to re-implement all algorithms using new data structures (daunting task) • Discovered rewriting AIGs • P. Bjesse and A. Boralv, "DAG-aware circuit compression for formal verification", Proc. ICCAD ’04, pp. 42-49. • Decided to try to keep all transformations fast and scalable • No BDDs • No SOPs • No Espresso

What Is Berkeley ABC? • A system for logic synthesis and verification • Fast • Scalable • High quality results (industrial strength) • Exploits synergy between synthesis and verification • A programming environment • Open-source • Evolving and improving over time

Design Flow Verification System Specification RTL ABC Logic synthesis Technology mapping Physical synthesis Manufacturing

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Combinational synthesis AIG rewriting technology mapping resynthesis after mapping Sequential synthesis retiming structural register sweep merging seq. equiv. nodes Areas Addressed by ABC • Formal verification • combinational equivalence checking • bounded sequential verification • unbounded sequential verification • equivalence checking using synthesis history

Subgraph 2 Subgraph 1 Subgraph 3 A A a a b c b a c a a c a b b c b c a Subgraph 2 Subgraph 1 B B a c b a c a b a c a b Subgraph 2 Subgraph 1 Combinational Synthesis • AIG rewriting minimizes the number of AIG nodes without increasing the number of AIG levels • Pre-computing AIG subgraphs • Consider function f = abc Rewriting AIG subgraphs Rewriting node A  Rewriting node B  In both cases 1 node is saved

f f e a c d b e a c d b Technology Mapping Input: A Boolean network (And-Inverter Graph) Output: A netlist of K-LUTs implementing AIG and optimizing some cost function Technology Mapping The subject graph The mapped netlist

Sequential Synthesis • Structural register sweep (scleanup) • Merge registers with identical drivers • Replace stuck-at registers by constants • Retiming (dretime) • Minimize the number of registers under delay constraints • Preserves equivalent initial state • Sequential SAT sweeping (scorr) • Detecting and merging sequencially equivalent nodes

Equivalence checking Property checking p 0 0 D2 D1 D1 Formal Verification • Equivalence checking • Takes two designs and makes a miter (AIG) • Model checking safety properties • Takes design and property and makes a miter (AIG) The goals are the same: to transform AIG until the output is proved constant 0 Breaking News: ABC won a model checking competition at CAV in August 2008

Model Checking Competition

5. ABC 238

Time (sec) ABC # problems solved

Command “dprove” in ABC Preprocessors • transforming initial state (“undc”, “zero”) • converting into an AIG (“strash”) • creating sequential miter (“miter -c”) • combinational equivalence checking (“iprove”) • bounded model checking (“bmc”) • sequential sweep (“scl”) • phase-abstraction (“phase”) • most forward retiming (“dret -f”) • partitioned register correspondence (“lcorr”) • min-register retiming (“dretime”) • combinational SAT sweeping (“fraig”) • for ( K = 1; K  16; K = K * 2 ) • signal correspondence (“scorr”) • stronger AIG rewriting (“dc2”) • min-register retiming (“dretime”) • sequential AIG simulation • interpolation (“int”) • BDD-based reachability (“reach”) • saving reduced hard miter (“write_aiger”) Combinational solver Fast engines Medium engines Slower Main induction loop Last-gasp engines

ABC vs. Other Tools • Industrial + well documented, fewer bugs - black-box, push-button, no source code, often expensive • SIS + traditionally very popular - data structures / algorithms outdated, weak sequential synthesis • VIS + very good implementation of BDD-based verification algorithms - not meant for logic synthesis, does not feature the latest SAT-based implementations • MVSIS + allows for multi-valued and finite-automata manipulation - not meant for binary synthesis, lacking recent implementations

Boolean network in SIS f f z z y x x y e a c d b e a b c d How Is ABC Different From SIS? Equivalent AIG in ABC AIG is a Boolean network of 2-input AND nodes and invertors (dotted lines)

One AIG Node – Many Cuts Combinational AIG • Manipulating AIGs in ABC • Each node in an AIG has many cuts • Each cut is a different SIS node • No a priori fixed boundaries • Implies that AIG manipulation with cuts is equivalent to working on many Boolean networks at the same time f e a c d b Different cuts for the same node

“Classical” synthesis Boolean network Network manipulation (algebraic) Elimination Factoring/Decomposition Speedup Node minimization Espresso Don’t cares computed using BDDs Resubstitution Technology mapping Tree based ABC“contemporary” synthesis AIG network DAG-aware AIG rewriting (Boolean) Several related algorithms Rewriting Refactoring Balancing Speedup Node minimization Boolean decomposition Don’t cares computed using simulation and SAT Resubstitution with don’t cares Technology mapping Cut based with choice nodes Comparison of Two Syntheses

Technology mapping with structural choices Cut-based, heuristic, good area/delay, flexible Combinational logic synthesis Fast, scalable, good quality Sequential verification Integrated, interacts with synthesis Sequential synthesis Innovative, scalable, verifiable Existing Capabilities (2005-2008) ABC

Overview • Introduction • What is ABC? • ABC fundamentals • Areas addressed by ABC • Synthesis • Technology mapping • Verification • Contrast with classical methods • How is ABC different from SIS? • Recent work • Speedup • Factoring • Don’t-care based optimization • Scalable sequential synthesis • WireMap • White boxes • Summary

Command “speedup” Timing Criticality • Critical nodes • Used by many traditional algorithms • Critical edges • Used by our algorithm • We pre-compute critical edges of critical nodes • Reduces computation • An edge between critical nodes may not be critical • See illustration: edge 13 Primary outputs 4 4 3 3 2 2 1 1 Primary inputs

Delay-Oriented Restructuring • Using traditional MUX-restructuring • AKA generalized select transform x and y are the critical edge inputs

Overall Algorithm mapped netlist performSpeedup ( subject graph S, // S is an And-Inverter Graph mapped netlist M, // M was previously derived by tech-mapping of S timing window w, // w is used to detect the critical paths logic depth l, // l is used to detect a logic cone rooted at a node edge count p ) // p limits the number critical edges of the cone { perform timing analysis of M with unit-delay or LUT-library model; pre-compute critical section of M as nodes n such that 0  slack(n)  w; pre-compute timing-critical edges connecting these nodes; for each timing critical node n { find cone C of M that extends l levels down from n; pick the set of timing-critical edges V feeding into C; if the number of edges in V exceeds p, continue; find logic cone C’ in S corresponding to C in M; find variables V’ in S corresponding to V in M; derive cofactors of the function of C’ w.r.t. variables in V’; build multiplexer tree C’’ of the cofactors using variables in V’; add structural choice C’= C’’ to the subject graph S; } returnmapped netlist M’ derived by mapping subject graph S with added choices; } Done only once

Experimental Results for “speedup” Time1 – the runtime of AIG restructuring only Time2 – the total runtime of Speedup Geomean – geometric averages of columns Ratios – ratios of geometric averages LUT – number of LUTs Lev – number of LUT levels Delay – delay using LUT library Total – total runtime of Baseline

BDD Basic Inner Core Algorithm (DSD) We use a fast disjoint support decomposition (DSD) algorithm as our underlying subroutine • follows Bertacco and Damiani, "The disjunctive decomposition of logic functions“, ICCAD '97 • but • uses heuristics to speed it up • no BDDs • uses truth tables • limit inputs to up to 16

E H C G 1 F D x5 x3 B c D x2 A x4 a c x1 a Disjoint Support Decomposition (DSD) (Simple Disjunctive Decomposition) Theorem 1 [Ashenhurst 1959]. For a completely specified Boolean function, there is a uniquemaximal DSD (up to the complementation of inputs and outputs and factoring of ANDs/ORs and XORs).

H 1 c D b a Non-Disjoint Decomposition Definition: A function F has an ( ) -decomposition if it can be written as where () is a partition of the variables x and D is a single output function. The variables in the set b are called the shared variables. The variables a are called the bound set and cthe free set.

E C G X D x3 x1 B Z Y x4 x5 A x2 W x2 x1 x4 x5 Non-Disjoint Decomposition Theorem2: A function has an - decomposition if and only ifeach of the cofactors of F with respect to has a DSD structure in which the variables are in a separate sub-tree.

Application of Factoring(uses Theorem 2) Rewriting a k-LUT mapped circuit. • For each LUT, and each cut of no more than 16 inputs, • express the output of the LUT as truth table in terms of the cut variables – F(x) • Find variables b such that its cofactors are support reducing • we exhaustively look for up to two variables in the b set • Take the best (a,b) set and decompose F=H(D(a,b),b,c) • Recursively decompose H and D if they do not fit into a k-LUT. • If improvement, replace LUTs in cut with its new decomposition. Experimental results later

Window POs m = 3 n = 3 Window PIs Windowing a Node in the Networkfor Don’t-Care Computation • Definition • A window for a node in the network is the context in which the don’t-cares are computed • A window includes • n levels of the TFI • m levels of the TFO • all re-convergent paths captured in this scope • Window with its PIs and POs can be considered as a separate network Boolean network (k-LUT mapped circuit)

Care Set Representation “Miter” constructed for the window POs If output is 1 then we care … Window Window Same window with inverter f f Window x x s

Resubstitution Resubstitution considers a node in a Boolean network and expresses it using a different set of fanins X X Computation can be enhanced by use of don’t cares

Resubstitution with Don’t-Cares Consider all or some nodes in Boolean network. For each node • Create window • Select possible fanin nodes (divisors) • For each candidate subset of divisors • Rule out some subsets using simulation • Check resubstitution feasibility using SAT • Compute resubstitution function using interpolation • A low-cost by-product of completed SAT proofs • Update the network if there is an improvement

g1 g1 g3 g3 g2 g2 C(x) F(x) F’(x) h(g) C(x) F(x) Resubstitution with Don’t Cares • Given: • node function F(x) to be replaced • care set C(x) for the node • candidate set of divisors {gi(x)} for re-expressing F(x) • Find: • A resubstitution function h(y) such that F(x) = h(g(x)) on the care set • SPFD Theorem: Function hexists if and only if every pair of care minterms, x1 and x2, distinguished by F(x), is also distinguished by gi(x) for some i

Miter for resubstitution check h(g) F F Checking Resubstitution using SAT SPFD theorem in practice • Note use of care set, C. • Resubstitution function exists if and only if SAT problem is unsatisfiable. • An h(g)is obtained by interpolation

Experimental Results

The Main Idea • Consider registers and nodes of a design • Detect candidate equivalences in this set using random/guided simulation • Prove candidates by K-step induction • Merge the resulting equivalences • This is a subset of sequential synthesis with • Practical advantages (does not move registers, etc) • Scales to large designs • Offers substantial improvements • Comes with a verification guarantee

SAT-1 SAT-1 SAT-3 A A A B B B SAT-4 SAT-2 SAT-2 C C C D D D Base Case Inductive Case ? Candidate equivalences: {A,B}, {C,D} ? Proving internal equivalences in a topological order in frame K ? ? PIk 0 0 PI1 C ? D A Assuming internal equivalences to in uninitialized frames 0 through K-1 ? B PI1 0 0 PI0 C D Initial state A B Proving internal equivalences in initialized frames 0 through K-1 PI0 Symbolic state

? A’ = B’ C = D A = B ? C’ D’ A’ B’ C’ = D’ One time-frame of the design C D A B C = D A = B Dynamic Partitioning(register correspondence) Illustration for two candidate equiv. classes: {A,B}, {C,D} Partition 1 Partition 2

Academic Benchmarks Columns “Baseline”, “Reg Corr” and “Sig Corr” show geometric means.

Industrial Benchmarks In case of multiple clock domains, optimization was applied only to the domain with the largest number of registers.

Reasons for Large Improvements • Redundancy introduced by HDL compilers • Early logic duplication by the designer • Accidental sequential redundancies • Sequential redundancies present due to reuse of design components that had more functionality than needed

Motivation Fewer pin-to-pin connections should make the design easier to place and route Newer FPGAs allow two outputs per LUT Thus fewer pin-to-pin connections should produce a mapping that “packs” better into dual-output LUTs

ABC: A System for Sequential Synthesis and Verification