ECE 667 Spring 2011 Synthesis and Verification of Digital Circuits

1. ECE 667Spring 2011Synthesis and Verificationof Digital Circuits Introduction to Logic Synthesis

2. HDL specification Front-end parsing Techn-independent optimization Technology mapping Cell library Manufacturing Synthesis Flow Logic synthesis ECE 667 - Synthesis & Verification

3. Specification a b Technology-Independent Optimization h module example(clk, a, b, c, d, f, g, h) input clk, a, b, c, d, e, f; output g, h; reg g, h; always @(posedge clk) begin g = a | b; if (d) begin if (c) h = a&~h; else h = b; if (f) g = c; else a^b; end else if (c) h = 1; else h ^b; end endmodule e 0 Logic Extraction Technology-Dependent Mapping a g1 G b g0 f g g G h5 d c f h3 d b H c clk e d h H a h1 e c f clk Synthesis Flow a multi-stage process

4. a b c d e f Data Flow Graph (DFG)

5. RTL to Network Transformation Technology independent Optimizations Technology Dependent Optimizations Technology Mapping Test Preparation Typical Synthesis Scenario - read HDL - control/data flow analysis - basic logic restructuring - crude measures for goals - use logic gates from target cell library - timing optimization - physically driven optimizations - improve testability - test logic insertion ECE 667 - Synthesis & Verification

6. Local versus Global Transformations • Local transformations optimize the function of one node of thenetwork • smaller area • better performance • map to a particular set of cells (library) • Global transformations restructure the entire network • merging nodes • spitting nodes • removing/changing connections between nodes • Node representation: • SOP, POS • BDD • Factored forms • keep size bounded to avoid blow-up of local transformations ECE 667 - Synthesis & Verification

7. Logic Optimization Two-level logic (PLA) Multi-level logic (standard cells) Heuristic (espresso) Exact (QM) Boolean Functional (BDD-based) Structural (SIS) Functional (AC, Kurtis) algebraic Logic Optimization methods Boolean ECE 667 - Synthesis & Verification

8. General Logic Structure Combinational logic (CL) Sequential elements • Combinational optimization • keep latches/registers at current positions, keep their function • optimize combinational logic in between • Sequential optimization • change latch position/function (retiming) ECE 667 - Synthesis & Verification

9. Given: Finite-State Machine F(X,Y,Z, , ) where: X Y D What is Logic Synthesis? X: Input alphabet Y: Output alphabet Z: Set of internal states : X x Z Z (next state function, Boolean) : X x Z Y (output function, Boolean) Combinational logic Sequential logic • Target: Circuit C(G, W) where: • G: set of circuit components • {Boolean gates, flip-flops, etc} • W: set of wires connecting G ECE 667 - Synthesis & Verification

10. Y=(y1,y2,…,yn) X=(x1,x2,…,xn) l S’=(s’1,s’2,…,s’n) S=(s1,s2,…,sn) d D Basic Model of Sequential circuit: FSM M(X,Y,S,S0,d,l): X: Inputs Y: Outputs S: Current State S0: Initial State(s) d: X ´ S ® S (next state function) l: X ´ S ® Y (output function) Sequential synthesis: find (multi-level) implementation of d (X) and l(X)that minimize its cost (area, delay, power) • Delay elements: • Clocked: synchronous • single-phase clock, multiple-phase clocks • Unclocked: asynchronous ECE 667 - Synthesis & Verification

11. Optimization Criteria for Synthesis The optimization criteria for logic optimization is to minimize some function of: • Area occupied by the logic gates and interconnect (approximated by literals = transistors in technology independent optimization) • Critical path delayof the longest path through the logic • Degree of testability of the circuit, measured in terms of the percentage of faults covered by a specified set of test vectors for an approximate fault model (e.g. single or multiple stuck-at faults) • Power consumed by the logic gates • Noise Immunity • Place-ability, Wire-ability while simultaneously satisfying misc. constraints ECE 667 - Synthesis & Verification

12. Two-Level (PLA) vs. Multi-Level E.g. Standard Cell Layout PLA • control logic • constrained layout • highly automatic • technology independent • multi-valued logic • input, output, state encoding Very predictable Multi-level Logic • all logic • general (standard cells, macro cells, blocks) • automatic • partially technology independent • part of multi-level logic Very hard to predict ECE 667 - Synthesis & Verification

13. Product terms x x 0 1 x 2 AND OR plane plane f f 0 1 x x x 0 1 2 Two-level Logic: the PLA ECE 667 - Synthesis & Verification

14. Two-Level Logic Minimization Every logic function can beexpressed in sum-of-productsformat (AND-OR) minterm Inverting format (NOR-NOR) more effective ECE 667 - Synthesis & Verification

15. Programmable Logic Array Pseudo-NMOS PLA V DD GND GND GND GND GND GND GND V X X X X X X f f 0 0 1 1 2 2 0 1 DD AND-plane OR-plane ECE 667 - Synthesis & Verification

16. Transformation-based Synthesis • All modern synthesis systems are build that way • Series of transformations that change network representation • work on uniform network representation • “script” of “scenario” that can combine those transformations to a overall greedy • Transformations differ in: • their scope • local versus global restructuring • the domain they optimize • combinational versus sequential • timing versus area • technology independent versus technology dependent • the underlying algorithms they use • BDD based, SAT based, structure based, etc. ECE 667 - Synthesis & Verification

17. Network Representation Boolean network: • directed acyclic graph (DAG) • node logic function representation fj(x,y) • node variableyj: yj= fj(x,y) • edge (i,j)if fjdepends explicitly on yi Inputs x = (x1, x2,…,xn ) Outputs z = (z1, z2,…,zp ) External don’t cares: d1(x), …, dp(x) ECE 667 - Synthesis & Verification

18. Sum of Products (SOP) Example: abc’+a’bd+b’d’+b’e’f (sum of cubes) Advantages: • easy to manipulate and minimize • many algorithms available (e.g. AND, OR, TAUTOLOGY) • two-level theory applies Disadvantages: • Not representative of logic complexity. For example: f = ad+ae+bd+be+cd+ce f’ = a’b’c’+d’e’ These differ in their implementation by an inverter. • Not easy to estimate logic size and performance • Difficult to estimate progress during logic manipulation ECE 667 - Synthesis & Verification

19. Factored Forms Example: (ad+b’c)(c+d’(e+ac’))+(d+e)fg Advantages • good representative of logic complexityf=ad+ae+bd+be+cd+ce f’=a’b’c’+d’e’  f=(a+b+c)(d+e) • in many designs (e.g. complex gate CMOS) the implementation of a function corresponds directly to its factored form • good estimator of logic implementation complexity • doesn’t blow up easily Disadvantages • not as many algorithms available for manipulation • hence often just convert into SOP before manipulation ECE 667 - Synthesis & Verification

20. Binary Decision Diagrams (BDDs) • Like factored form, represents both function and complement • Like network of muxes, but restricted since controlled by primary input variables • not really a good estimator for implementation complexity • Given an ordering, reduced BDD is canonical, hence a good replacement for truth tables • For a good ordering, BDDs remain reasonably small for complicated functions (e.g. not multipliers) • Manipulations are well defined and efficient • True support (dependency) is displayed ECE 667 - Synthesis & Verification

21. f f g g AND-INVERTER Graphs (AIG) • Base data structure uses two-input AND function for vertices and INVERTER attributes at the edges (individual bit) • use De’Morgan’s law to convert OR operation etc. • Hash table to identify and reuse structurally isomorphic circuits Means complement ECE 667 - Synthesis & Verification