Designing Combinational Logic Circuits: Part2 Alternative Logic Forms: Ratio Logic

1. Designing CombinationalLogic Circuits: Part2 Alternative Logic Forms: Ratio Logic Pass-Transistor Dynamic Logic

2. V V V DD DD DD Resistive Depletion PMOS Load V < 0 R Load Load T L V SS F F F In In In 1 1 1 In In In PDN PDN PDN 2 2 2 In In In 3 3 3 V V V SS SS SS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Ratio Logic Goal: to reduce the number of devices over complementary CMOS

3. V DD • N transistors + Load Resistive • V = V OH DD Load R L R • V = PN OL R + R F PN L In 1 • Assymetrical response In PDN 2 In • Static power consumption 3 • t = 0.69 R C pL L L V SS Ratio Logic

4. V V DD DD Depletion PMOS V < 0 Load Load T V SS F F In In 1 1 In In PDN PDN 2 2 In In 3 3 V V SS SS depletion load NMOS pseudo-NMOS Active Loads

5. Pseudo-NMOS

6. 3.0 2.5 W/L = 4 2.0 p 1.5 [V] W/L = 2 t u p o V 1.0 W/L = 0.5 W/L = 1 p p 0.5 W/L = 0.25 p 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V [V] in Pseudo-NMOS VTC

7. V DD M 1 M 1 >> M 2 Enable M 2 F C L A B C D Adaptive Load Improved Loads

8. V V DD DD M1 M2 Out Out A A PDN1 PDN2 B B V V SS SS Differential Cascode Voltage Switch Logic (DCVSL) Even Better Noise Immunity

9. Out Out B B B B A A XOR-NXOR gate DCVSL Example

10. 2.5 1.5 0.5 -0.5 0 0.2 0.4 0.6 0.8 1.0 DCVSL Transient Response A B [V] e A B g a t l o A , B V A,B Time [ns]

11. B Out A Switch s Out t u p Network B n I A Pass-Transistor Logic • N transistors • No static consumption

12. Example: AND Gate

13. NMOS-Only Logic 3.0 In Out 2.0 [V] x e g a t l o V 1.0 0.0 0 0.5 1 1.5 2 Time [ns]

14. NMOS-only Switch V C = 2.5 V C = 2.5 M 2 A = 2.5 V B A = 2.5 V M n B M C 1 L V does not pull up to 2.5V, but 2.5V - V TN B Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect)

15. NMOS Only Logic: Level Restoring Transistor V DD V DD Level Restorer M r B M 2 X M A Out n M 1 • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem

16. 2.0 1.0 0.0 0 100 200 300 400 500 Restorer Sizing 3.0 • Upper limit on restorer size • Pass-transistor pull-downcan have several transistors in stack W / L =1.75/0.25 [V] r e W / L =1.50/0.25 g r a t l o V W / L =1.25/0.25 W / L =1.0/0.25 r r Time [ps]

17. Solution 2: Single Transistor Pass Gate with VT=0 V DD V DD 0V 2.5V Out 0V V DD 2.5V WATCH OUT FOR LEAKAGE CURRENTS

18. Complementary Pass Transistor Logic

19. Solution 3: Transmission Gate C C A A B B C C C = 2.5 V A = 2.5 V B C L C = 0 V

20. Resistance of Transmission Gate

21. S S Pass-Transistor Based Multiplexer S VDD GND In1 In2 S

22. Transmission Gate XOR B B M2 A A F M1 M3/M4 B B

23. 2.5 2.5 2.5 2.5 V V V V V V 1 i n-1 i-1 i+1 n In C C C C C 0 0 0 0 (a) R R R R eq eq eq eq V V V V V 1 n-1 i i+1 n In C C C C C (b) R R R eq eq eq C C C C Delay in Transmission Gate Networks m R R R eq eq eq In C C C C (c)

24. Delay Optimization

25. Transmission Gate Full Adder Similar delays for sum and carry

26. Dynamic Logic

27. Dynamic CMOS • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

28. Clk Mp ((AB)+C) Out CL A C B Clk Me Dynamic Gate off Clk Mp on 1 Out In1 In2 PDN In3 Clk Me off on Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

29. Conditions on Output • Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. • Inputs to the gate can make at most one transition during evaluation. • Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL

30. Properties of Dynamic Gates • Logic function is implemented by the PDN only • number of transistors is N + 2 (versus 2N for static complementary CMOS) • Full swing outputs (VOL = GND and VOH = VDD) • Non-ratioed - sizing of the devices does not affect the logic levels • Faster switching speeds • reduced load capacitance due to lower input capacitance (Cin) • reduced load capacitance due to smaller output loading (Cout) • no Isc, so all the current provided by PDN goes into discharging CL

31. Properties of Dynamic Gates • Overall power dissipation usually higher than static CMOS • no static current path ever exists between VDD and GND (including Psc) • no glitching • higher transition probabilities • extra load on Clk • PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL equal to VTn • low noise margin (NML) • Needs a precharge/evaluate clock

32. CL Issues in Dynamic Design 1: Charge Leakage CLK Clk Mp Out A Evaluate VOut Clk Me Precharge Leakage sources Dominant component is subthreshold current

33. CL Solution to Charge Leakage Keeper Clk Mp Mkp A Out B Clk Me Same approach as level restorer for pass-transistor logic

34. CL CA CB Issues in Dynamic Design 2: Charge Sharing Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness Clk Mp Out A B=0 Clk Me

35. Cd=10fF CL=50fF Cb=15fF Cc=15fF Ca=15fF Charge Sharing Example Clk Out A A B B B !B C C Clk

36. Charge Sharing V DD M Clk p Out C L M A a X C a M = B 0 b C b M Clk e

37. Solution to Charge Redistribution Clk Clk Mp Mkp Out A B Clk Me Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

38. CL1 CL2 Issues in Dynamic Design 3: Backgate Coupling Clk Mp Out1 =1 Out2 =0 In A=0 B=0 Clk Me Dynamic NAND Static NAND

39. Backgate Coupling Effect Out1 Voltage Clk Out2 In Time, ns

40. CL Issues in Dynamic Design 4: Clock Feedthrough Coupling between Out and Clk input of the precharge device due to the gate to drain capacitance. So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out. Clk Mp Out A B Clk Me

41. Clock Feedthrough Clock feedthrough Clk Out In1 In2 In3 In & Clk Voltage In4 Out Clk Time, ns Clock feedthrough

42. Other Effects • Capacitive coupling • Substrate coupling • Minority charge injection • Supply noise (ground bounce)

43. Clk In VTn Out1 V Out2 Cascading Dynamic Gates V Clk Clk Mp Mp Out2 Out1 In Clk Clk Me Me t Only 0  1 transitions allowed at inputs!

44. Domino Logic Clk Mp Mkp Clk Mp Out1 Out2 1  1 1  0 0  0 0  1 In1 In4 PDN In2 PDN In5 In3 Clk Me Clk Me

45. Ini Ini Ini Ini PDN PDN PDN PDN Inj Inj Inj Inj Why Domino? Clk Clk Like falling dominos!

46. Properties of Domino Logic • Only non-inverting logic can be implemented • Very high speed • static inverter can be skewed, only L-H transition • Input capacitance reduced – smaller logical effort

47. Designing with Domino Logic V V DD DD V DD Clk M Clk M p p M r Out1 Out2 In 1 PDN In PDN In 2 4 In 3 Can be eliminated! M Clk M Clk e e Inputs = 0 during precharge

48. Footless Domino The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit current A solution is to delay the clock for each stage

49. Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B Clk Me Solves the problem of non-inverting logic

50. np-CMOS Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me Only 0  1 transitions allowed at inputs of PDN Only 1  0 transitions allowed at inputs of PUN