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ENEL619.23 DSP Architectures

ENEL619.23 DSP Architectures. Tiger SHARC Memory Operations. Overview. Architecture Overview IALU Features Data addressing Normal, broadcast, merged distribution Circular buffers DAB Bit reversing Parallel instructions. References.

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ENEL619.23 DSP Architectures

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  1. ENEL619.23 DSP Architectures Tiger SHARC Memory Operations Tiger SHARC Memory Operations REV B

  2. Overview • Architecture Overview • IALU Features • Data addressing • Normal, broadcast, merged distribution • Circular buffers • DAB • Bit reversing • Parallel instructions Tiger SHARC Memory Operations REV B

  3. References • ADSP-TS101 TigerSHARC Processor Programming Reference, Rev 1, January 2003, Analog Devices. – Sections 1 and 6 • A number of the figures in this presentation are based on figures found in the ADSP-TS101 TigerSHARC Processor Programming Reference. Tiger SHARC Memory Operations REV B

  4. X Compute Block X Register File 32 x 32 bit SDRAM Controller & External Port Interfaces Y Register File 32 x 32 bit DMA and Link Controllers Y Compute Block Architecture Overview Access to program and two data operands without memory or bus constraints. Tiger SHARC Memory Operations REV B

  5. IALU Features • 31 32 bit general registers + 1 status register + 8 dedicated registers for circular buffers • Performs integer ALU operations and data addressing • ALU instructions: ADD, SUB, ARS, LRS (right shifts only), ROT (left and right), AND NOT, NOT, OR, XOR, ABS, MIN, MAX, CMP • Status flags: zero (Z), negative (N), overflow (V), carry (C) • Instruction conditions: EQ, LT, LE, NEQ, NLT, NLE • Instruction options: unsigned (U), circular buffer (CB), bit reverse (BR), computed jump (CJMP) • Address related operations: data address generation, circular buffers, bit reverse, UREG moves, DAB control. Tiger SHARC Memory Operations REV B

  6. Indirect Loads and Stores • Absolute: • Immediate: XR0 = [0x34FFFFFC];; • Register + optional immediate or register update: XR0 = [J0];; XR0 = [J0 += 0x4];; XR0 = [J0 += J1];; Relative offset: • Immediate offset XR0 = [J0 + 0x34FFFFFC];; • Register offset XR0 = [J0+J1];; Tiger SHARC Memory Operations REV B

  7. Immediate Extension Operations • Provides capability for 32 bit immediate operands. • Assembler automatically uses 2nd instruction slot (programmer must only use 3 of the 4 instruction slots) • Requires the instruction with immediate extension to be in the 1st slot • Example: XR0 = [0x34FFFFFC]; K2=[K1+1]; YR0 = YR1 +YR2;; • Only 1 immediate extension allowed per instruction line • Don’t have to use 32 bit immediate. An 8 bit immediate will fit into the 32 bit instruction. (15 bit immediate for Ureg direct load instructions) Tiger SHARC Memory Operations REV B

  8. Normal, Broadcast, Merged Distribution Tiger SHARC Memory Operations REV B

  9. Word DAB J1 = 0x00200001 First access loads in nearest quad boundary Second access loads in correct value Tiger SHARC Memory Operations REV B

  10. Short Word DAB J0 = ADDRESS(iaInput);; J0 = J0 +5; XR3:0 = SDAB Q[J0 += 8];; XR3:0 = SDAB Q[J0 += 8];; Can realign on 16 bit boundaries Tiger SHARC Memory Operations REV B

  11. Circular Buffers • Implemented with index, modify, length and base registers • Index registers must be from J3~J0 or K3 ~ K0 • Modify register can be any register in the same IALU • Length and base registers are dedicated registers JL3 ~ JL0 and JB3 ~ JB0 respectively. Tiger SHARC Memory Operations REV B

  12. Circular Buffer Code Example JL = 0;; JB = 0x34FFFFC0; // need 4 cycle latency J0 = 0x34FFFFC0; // before using JL or JB J1 = 1; NOP NOP XR0 = CB [J0 += J1];; XR1 = CB [J0 += J1];; XR2 = CB [J0 += J1];; XR3 = CB [J0 += J1];; // J0 = JB after this instr. Tiger SHARC Memory Operations REV B

  13. Bit Reverse .section data1 .var intput[8] = {0, 1, 2, 3, 4, 5, 6, 7}; .section program J0 = ADDRESS(input); XR0 = BR[J0 += 0x2121] /* If we assume that “input” is located at 0x0200A5A5 then Data is loaded from 0x02009454 Instead of 0x0200C6C6 Tiger SHARC Memory Operations REV B

  14. IALU Instructions ALU Instructions Dreg indirect register stores Ureg indirect register load Ureg indirect register stores Dreg indirect register load and DAB ops Ureg register transfer Tiger SHARC Memory Operations REV B

  15. Parallel Instructions • A couple of examples of restrictions from the over 20 restrictions that apply to IALU instructions: • Loading from and storing to the same register in the same instruction line gives unpredictable results • A line of instructions can contain at most 1 load immediate data to register or 1 Ureg to Ureg transfer • Details of restrictions can be found on pages 1-36 to 1-46 of the TigerSHARC Programming Reference • Resource tables on 1–29 to 1–35 can help sort out resource restrictions for a single instruction line • Consider the following instruction: • [J0+J4] = XR1; [K8+=k9]=XR3;; Tiger SHARC Memory Operations REV B

  16. [J0+J4] = XR1; [K8+=k9]=XR3;; Tiger SHARC Memory Operations REV B

  17. [J0+J4] = XR1; [K8+=k9]=XR3;; Tiger SHARC Memory Operations REV B

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