Introduction to VHDL

1. Introduction to VHDL By Mr. Fazrul Faiz Zakaria School of Computer and Communication Engineering UniMAP

2. VHDL ??? Very Hard Difficult Language VHSICHardware Description Language Very High Speed Integrated Circuits VHDL is an IEEE standard

3. Why VHDL? • HDL is a software solution due to limits in hardware solutions and to: • Increasing design complexity • Increasing cost in time and investment • Increasing knowledge requirement • Inadequacy of other existing languages

4. VHDL main Features • Supports the whole design process: • system level • RT level • logic level • circuit level (to some extent) • Suitable for specification in • behavioral domain • structural domain • Precise simulation semantics is associated with the language constructs

5. outputs if (shift_left) for (j=0; j<8; j=j+1) #5 out[j]=out[j-1]; else for (j=0; j<8; j=j+1) #5 out[j] = out[j+1]; Behavioral Modeling • Only the functionality of the circuit, no structure • Synthesis tool creates correct logic • For the purpose of synthesis as well as simulation Input

6. Higher-level Component output1 input1 Lower-level Component1 Lower-level Component1 outputn inputn Structural Modeling • Functionality and structure of the circuit • Call out the specific hardware • For the purpose of synthesis

7. VHDL Architectures Abstraction Levels VHDL Architectures Algorithmic How it works FSM Behavioral RTL Structural How it is connected Gate Layout

8. Basic VHDL Modeling Structure Library / Package Declaration Entity Declaration Architecture Flow

9. LIBRARY / PACKAGE DECLARATION library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library work; use work.my_package.entity_name; use work.my_package.function_name;

10. Entity Declaration • Specifies the input and output signals of the entity • modes : in, out, inout, buffer • Format : Entitynameis port(port_name : mode data_type); Endname;

11. Entity Declaration (2) entity name port names port mode (direction) entityreg4 isport ( d0, d1, d2, d3, en, clk : inbit; q0, q1, q2, q3 : outbit);end entityreg4; punctuation reserved words port type

12. Rules for Entity Name • Any alphanumeric character may be used in the name, as well as the ‘_’ underscore character. • It is not case sensitive • Cannot be a VHDL keyword • Cannot begin with a number, must begin with a letter • Cannot have 2 straight ‘_ _’ underscores • Cannot end with an ‘_’ underscore • Cannot have a blank space

13. ARCHITECTURE • The Internal Aspect of a Design Unit • Can be behavioral (RTL) or structural • Always associated with single entity • Single entity can have multiple architectures architecturearchitecture_nameofentity_nameis {architecture_declarative_part} begin {architecture_descriptive_part} end[architecture_name];

14. Operators

15. Architecture : Behavioral Modeling • Architecture body • describes an implementation of an entity • may be several per entity • Behavioral architecture • describes the algorithm performed by the module • contains • process statements, each containing • sequential statements, including • signal assignment statements and • wait statements

16. Architecture : Behavioral Modeling architecturebehavof reg4 isbegin process (d0, d1, d2, d3, en, clk) variable stored_d0, stored_d1, stored_d2, stored_d3 : bit;beginif en = '1' andclk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3;end if; q0 <= stored_d0 after 5 ns; q1 <= stored_d1 after 5 ns; q2 <= stored_d2 after 5 ns; q3 <= stored_d3 after 5 ns;end process; end behav; sensitivity list notice := syntax used for equating values from signals... simulates real-world propagation delays.

17. Behavioral Way’s Example

18. Behavioral Way’s Example (2)

19. Architecture : Structural Modeling • Structural architecture • implements the module as a composition of subsystems • contains • signal declarations, for internal interconnections • the entity ports are also treated as signals • component instances • instances of previously declared entity/architecture pairs • port maps in component instances • connect signals to component ports

20. Structural way’s example

21. Structural way cont.. • First declare D-latch and and-gate entities and architectures entityd_latchisport ( d, clk : in bit; q : out bit );end entityd_latch; architecture basic ofd_latchisbegin process (clk, d)beginifclk = ‘1’ then q <= d after 2 ns;end if;end process; end basic; entity and2 isport ( a, b : in bit; y : out bit );end entity and2; architecture basic of and2 isbegin process (a, b)begin y <= a and b after 2 ns;end process ; end basic;

22. Structural way... • Declare corresponding components in register architecture body architecturestructof reg4 is componentd_latchport ( d, clk : in bit; q : out bit );end component; component and2port ( a, b : in bit; y : out bit );end component; signalint_clk : bit; ...

23. Structural way.. • Now use them to implement the register ... begin bit0 : d_latchport map ( d0, int_clk, q0 ); bit1 : d_latchport map ( d1, int_clk, q1 ); bit2 : d_latchport map ( d2, int_clk, q2 ); bit3 : d_latchport map ( d3, int_clk, q3 ); gate : and2port map ( en, clk, int_clk ); end struct;

24. Mixed Behavior and Structure • An architecture can contain both behavioral and structural parts • process statements and component instances • collectively called concurrent statements • processes can read and assign to signals • Example: register-transfer-level (RTL) Model • data path described structurally • control section described behaviorally

25. Mixed Example

26. Mixed Example entity multiplier isport ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer );end multiplier; architecture mixed ofmulitplieris signalpartial_product, full_product : integer;signalarith_control, result_en, mult_bit, mult_load : bit; begin arith_unit : entitywork.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product, sum => partial_product,add_control => arith_control ); result : entity work.reg(behavior)port map ( d => partial_product, q => full_product, en => result_en, reset => reset ); ...

27. Mixed Example … multiplier_sr : entitywork.shift_reg(behavior)port map ( d => multiplier, q => mult_bit, load => mult_load, clk => clk ); product <= full_product; process (clk, reset) -- variable declarations for control_section -- …begin -- sequential statements to assign values to control signals -- …end process; end mixed;

28. Concurrent vs Sequential • Behavioral part for a combinational system divided into 2 categories • Concurrent assignment statements • Simple signal assignment • Conditional signal assignment (when…else) • Selected signal assignment (with…select) • Sequential assignment statements • If statement (if…then…else) • Case statement (case…when) • Loop statement (For-Loop & While-Loop)

29. Concurrent Assignment Statements • Defines an interconnected block by assigning values to signals • Executes continuously • Order of statements in a body is not affected • Eg : signal_name <= expression;

30. “when…else” Statements Architecture beh of dec_norm_we is Begin I0 <= ‘1’ when D = “00” else ‘0’; I1 <= ‘1’ when D = “01” else ‘0’; I2 <= ‘1’ when D = “10” else ‘0’; I3 <= ‘1’ when D = “11” else ‘0’; End beh;

31. “when…else” Statements Entity dec_we is Port( D : in std_logic_vector(1 downto 0); I : out std_logic_vector(3 downto 0)); End dec_we; Architecture beh of dec_we is Begin I <= “0001” when D=“00” else “0010” when D=“01” else “0100” when D=“10” else “1000” when D=“11”; End beh;

32. “with…select” Statements Architecture beh of dec_sel is Begin with D select I <= “0001” when “00”, “0010” when “01”, “0100” when “10”, “1000” when “11”; End beh;

33. Sequential Assignment Statements • The order of the statements is significant and can affect the semantics of the code • To differentiate from concurrent assignment, sequential assignment must be separated • Sequential assignments are enclosed inside a “process statement” to distinguish from concurrent assignments

34. “if…then…else” Statements Architecture beh of dec_if is Begin process (D) begin if D=“00” then I <= “0001”; elsif D=“01” then I <= “0010”; elsif D=“10” then I <= “0100”; else I <= “1000”; end if; end process; End beh;

35. “case…when” Statements Architecture beh of dec_cs is Begin process (D) begin case (D) is when “00” => I <= “0001”; when “01” => I <= “0010”; when “10” => I <= “0100”; when “11” => I <= “1000”; end case; end process; End beh;

36. Loop Statements Library ieee; Use ieee.std_logic_1164.all; Entity numbits is Port( D : in std_logic_vector(1 to 3); count : out integer range 0 to 3); End numbits; Architecture beh of numbits is Begin process (D) variable tmp : integer; begin tmp := 0; for i in 1 to 3 loop if D(i) = ‘1’ then tmp := tmp + 1; end if; end loop; count <= tmp; end process; End beh;

37. Mixed Behavioral Statements • Processes are concurrent • Sequential activity within each process Nesting of statements : • Concurrent statements in a concurrent statement • Sequential statements in a concurrent statement • Sequential statements in a sequential statement

38. Requirements RTL Model Simulate Synthesize Gate-levelModel Simulate Test Bench ASIC or FPGA Place & Route TimingModel Simulate Basic Design Methodology