Introduction to VHDL

1. Introduction to VHDL Joseph Collins, 3A Software Eng. with files from Dr. W.D. Bishop, P.Eng Email: j4collin@engmail.uwaterloo.ca

2. What is VHDL? • Very High-Speed Integrated Circuit • Hardware • Description • Language • A popular tool for designing digital hardware

3. Important Concepts • Entity • What the hardware looks like to the outside world • Defines inputs and outputs ENTITY lab1 IS PORT ( r1, r0 : in std_logic; x, y, z : in std_logic; a, d0, d1 : out std_logic ); END lab1;

4. Important Concepts • Architecture • This is the implementation of your entity. • This is where you put your gates and stuff. ARCHITECTURE main OF lab1 IS SIGNAL temp : std_logic; BEGIN a <= r0 AND r1; temp <= y OR z; d0 <= x AND temp; d1 <= (r0 AND x) OR temp; END main;

5. VHDL Data Types • std_logic • A wire • Can be set to ‘1’ or ‘0’ (among other things) • SIGNAL a : std_logic; • use ieee.std_logic_1164.all

6. VHDL Data Types • std_logic_vector • A group of wires with a similar purpose • SIGNAL v : std_logic_vector (3 DOWNTO 0); • Wires can be assigned: • individually: v(3) <= ‘0’; • in groups: v(1 DOWNTO 0) <= v(3 DOWNTO 2); • all at once: v <= “1001”; • use ieee.std_logic_1164.all

7. VHDL Data Types • signed/unsigned • Used to represent signed and unsigned numbers • SIGNAL num : signed (2 downto 0); • Assignment similar to std_logic_vectors • Can do arithmetic on these • This includes, addition, subtraction, multiplication, and comparisons • use ieee.numeric_std.all

8. Converting Between Data Types • One can convert between signed, unsigned and std_logic_vector explicitly • SIGNAL x : std_logic; • SIGNAL num : unsigned (3 DOWNTO 0); • SIGNAL v : std_logic_vector (3 DOWNTO 0); • … • num <= unsigned(v); • v <= std_logic_vector(num); • x <= v(1);

9. Combinational Circuitry • Statements that may be helpful • When-else statements • Case statements --a is std_logic, b is std_logic_vector (3 DOWNTO 0) --x and s are unsigned (3 DOWNTO 0) s <= x – 10; b <= “0000” WHEN a = ‘1’ ELSE std_logic_vector(x) WHEN x < 10 ELSE std_logic_vector(s); s <= x – 10; WITH x(3 DOWNTO 1) SELECT b <= std_logic_vector(s) WHEN “101” | “110” | “111”, std_logic_vector(x) WHEN OTHERS;

10. What questions do you have so far?

11. Processes • So far, we’ve covered basic combinational circuitry • Processes allow for much more human-readable designs • Processes can be combinational or sequential • Will not cover combinational because they are frowned upon by SE141 TAs

12. Sequential Processes • Sequential processes run on a clock signal • Usually involve one or more flip-flops • They are NOT sequential in the sense that the hardware will execute one step at a time • Hardware runs in parallel • You can make things run sequentially by separating tasks into multiple clock cycles.

13. D Flip-Flop with Chip Enable • Probably the second-simplest sequential process you will ever run into PROCESS BEGIN WAIT UNTIL RISING_EDGE(clock); IF (ce = ‘1’) THEN q <= d; END IF; END PROCESS;

14. State Machines • Flip Flops that represent a state in your system • Multiple encoding types • One-hot • Gray • Binary • Usually used in sequential processes

15. What questions do you have?

16. Hardware Interfacing • You can easily use a provided piece of hardware as part of a larger circuit • Make sure you understand the specs • You needn’t know the VHDL code behind this piece of hardware • This allows you to work independently on separate parts of your lab

17. Interfacing a Block of Memory • We wish to integrate a piece of 256x256 memory into our circuit ARCHITECTURE main OF circ IS COMPONENT mem IS PORT ( i_add : in std_logic_vector (7 DOWNTO 0); i_wren : in std_logic; i_clock : in std_logic; i_data : in std_logic_vector (7 DOWNTO 0); o_q : out std_logic_vector (7 DOWNTO 0) ); END COMPONENT mem; SIGNAL address, data, q : std_logic_vector (7 DOWNTO 0); SIGNAL wren, clk : std_logic; BEGIN … mem1: mem PORT MAP (address, wren, clk, data, q); … END main

18. Simulation • We have covered hardware that you can synthesize nicely for use on an FPGA board • VHDL can be used to simulate these circuits • Note: we will be using non-synthesizable VHDL for doing simulations

19. How to Simulate • Develop your simulation plan • Prepare a new entity and do a port map • Use wait statements to assign your inputs clock_proc: PROCESS BEGIN -- 50 MHz clock clk <= ‘0’; wait for 10 ns; clk <= ‘1’; wait for 10 ns; END PROCESS

20. Simulation Example ENTITY tb_lab1 IS END tb_lab1 ARCHITECTURE main OF tb_lab1 IS COMPONENT lab1 IS PORT ( r0, r1, x, y, z : in std_logic; a, d0, d1 : out std_logic ); END COMPONENT lab1; SIGNAL r0, r1, x, y, z, a, d0, d1 : std_logic; BEGIN lab1_inst : lab1 PORT MAP (r0, r1, x, y, z, a, d0, d1); r0_proc : PROCESS BEGIN r0 <= ‘0’; wait for 10 ns; r0 <= ‘1’; wait for 10 ns; END PROCESS; r1_proc : PROCESS BEGIN r1 <= ‘0’; wait for 20 ns; r1 <= ‘1’; wait for 20 ns; END PROCESS; --etc. END main;

21. What questions do you have?

22. Common Pitfalls • Multiple Signal Drivers • When you assign to a signal in multiple locations (without appropriate ifs) • Usually in multiple processes • Best preventative measure: avoid assigning to more than one signal in a given process • Processes run parallel to each other

23. Common Pitfalls • Invalid State = Undefined Behaviour • If your state machine enters an invalid state, it should return to a pre-defined “reset” state • This can happen by programmer error or due to environmental factors

24. What questions do you have? This is about all I have.

25. Do not hesitate to contact me! - Email: j4collin@engmail.uwaterloo.ca - I often hang out in SE lounge/lab and/or MathSoc (MC 3038) - Have a good Pi Day tomorrow