Introduction to VHDL

1. Introduction to VHDL Discussion D1.0

2. VHDL • VHDL is an international IEEE standard specification language (IEEE 1076-1993) for describing digital hardware used by industry worldwide • VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language • VHDL enables hardware modeling from the gate to system level • VHDL provides a mechanism for digital design and reusable design documentation

3. VHDL’s History • Very High Speed Integrated Circuit (VHSIC) Program • Launched in 1980 • Aggressive effort to advance state of the art • Object was to achieve significant gains in VLSI technology • Need for common descriptive language • $17 Million for direct VHDL development • $16 Million for VHDL design tools • Woods Hole Workshop • Held in June 1981 in Massachusetts • Discussion of VHSIC goals • Comprised of members of industry, government, and academia

4. VHDL’s History (Cont.) • In July 1983, a team of Intermetrics, IBM and Texas Instruments were awarded a contract to develop VHDL • In August 1985, the final version of the language under government contract was released: VHDL Version 7.2 • In December 1987, VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard • In September 1993, VHDL was restandardized to clarify and enhance the language • VHDL has been accepted as a Draft International Standard by the IEC

5. Additional Benefits of VHDL • Allows for various design methodologies • Provides technology independence • Describes a wide variety of digital hardware • Eases communication through standard language • Allows for better design management • Provides a flexible design language • Has given rise to derivative standards : • WAVES, VITAL, Analog VHDL

6. Architectural Structural Behavioral Algorithmic Processor Functional Block Systems Hardware Modules Algorithms Logic ALUs, Registers Register Transfer Gates, FFs Circuit Logic Transistors Transfer Functions Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions Physical/Geometry Gajski and Kuhn’s Y Chart [Smith88]

7. Levels of Abstraction Architectural Level • Behavioral domain • Set of performance specifications • Gross operation characteristics • Structural domain • Processors, memory units, device controllers, etc. communicating via ports or buses • Physical domain • High-level physical partitioning, such as chip or cabinet level

8. Levels of Abstraction Algorithmic Level • Behavioral domain • Complex algorithmic expressions, data structures, procedures, etc., which may include timing information • Description in a programming language such as C, Ada, or VHDL with support for concurrency and an appropriate timing model • Structural domain • Hardware modules to represent processes of behavioral domain • Physical domain • Clustering of operators into physical subsystems

9. Levels of AbstractionFunctional Block Level • Behavioral domain • Also known as Register Transfer Level • Arithmetic or logical expressions and transfers between registers • Structural domain • Functional units such as ALUs, MUXs, adders, and registers • Physical domain • Floorplanning or layout information for components of structural domain

10. Levels of AbstractionLogic Level • Behavioral domain • Also known as Gate Level • Boolean equations and finite automata • Structural Level • Gates, Flip-flops, and registers • Physical domain • Realizable hardware, such as TTL-based components

11. Levels of AbstractionCircuit Level • Behavioral domain • Differential equations used to describe circuit behavior • Structural domain • Circuit components such as transistors, resistors, etc. • Physical domain • Exact geometries for circuit components

12. Architectural Structural Behavioral Algorithmic Processor Functional Block Systems Hardware Modules Algorithms Logic ALUs, Registers Register Transfer Gates, FFs Circuit Logic Transistors Transfer Functions Rectangles Cell, Module Plans Floor Plans Clusters Physical Partitions Physical/Geometry The Role of Synthesis • In the context of the abstractions and domains just described, synthesis can be defined as: • A few-to-many translation from the Behavioral Domain to the Structural Domain • A few-to-many translation from the Structural Domain to the Physical Domain • A few-to-many translation from higher level of abstraction in one domain to a lower level of abstraction in the same or another domain

13. Synthesis Categories • Algorithm synthesis • Synthesis from design requirements to control-flow behavior or abstract behavior • Largely a manual process • Register-transfer synthesis • Also referred to as “high-level” or “behavioral” synthesis • Synthesis from either abstract behavior, control-flow behavior, or register-transfer behavior to register-transfer structure • Logic synthesis • Synthesis from register-transfer structures or Boolean equations to gate-level logic (or physical implementations using a predefined cell or IC library) [Parker84]

14. Synthesis Process Overview Specification Implementation Behavioral Functional Behavioral Simulation Behavioral Synthesis Optional RTL Simulation RTL Functional Synthesis & Test Synthesis Verification Gate-Level Simulation Gate-Level Analysis Gate Silicon Vendor Layout Place & Route Synopsys, Inc. Silicon