2. Single Cycle Implementation: Cycle 1 Cycle 2 Clk lw sw Waste Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw sw R-type IF ID EX MEM WB IF ID EX MEM IF Single Cycle vs. Multiple Cycle Multiple Cycle Implementation:

3. General Definitions • Latency: time to completely execute a certain task • E.g., time to read a sector from disk is disk access time or disk latency • Throughput: amount of work that can be done over a period of time

4. IF IF IF EX EX EX MEM MEM MEM WB WB WB A Pipelined MIPS Processor • Start the next instruction before the current one has completed • improves throughput • instruction latency is not reduced • clock cycle (pipeline stage time) limited by slowest stage • for some instructions, some stages are wasted cycles Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 ID lw ID sw ID R-type

5. Single Cycle Implementation: Cycle 1 Cycle 2 Clk lw sw Waste Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk lw sw R-type IF ID EX MEM WB IF ID EX MEM IF Pipeline Implementation: IF ID EX MEM WB lw IF ID EX MEM WB sw IF ID EX MEM WB R-type Single Cycle vs. Multiple Cycle vs. Pipelined Multiple Cycle Implementation:

6. Theoretical Performance • An ideal pipeline divides a task into k independent sequential subtasks • Each subtask requires 1 time unit to complete • The task itself requires k time units to complete • For n iterations of task, the execution times: • With no pipelining: nk time units • With pipelining: k + (n-1) time units • Speedup of a k-stage pipeline is • S = nk / [k+(n-1)] ==> k (for large n)

9. Simplified MIPS Pipelined Datapath Why are we duplicating some functional units? Can you foresee any problems with these right-to-left flows?

10. Pipeline registers • Need registers between stages • To hold information produced in previous cycle

11. IF

12. ID

13. EX for Load

14. MEM for Load

15. WB for Load There is a BUG here Wrongregisternumber

16. Corrected Datapath for Load