Chapter 9 Counters and Shift Registers
Counters and Shift Registers • Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. • Shift Register: A Sequential Circuit that moves stored data bits in a specific direction. Used in Serial Data Transfers, SIPO/PISO Conversions, Arithmetic, and Delays.
Counter Terminology – 1 • A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances on state for each clock pulse. • State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter.
Counter Terminology – 2 • Count Sequence: The specific series of output states through which a counter progresses. • Modulus: The number of states a counter sequences through before repeating (mod-n). • Counter directions: • UP - count high to low (MSB to LSB) • DOWN - count low to high (LSB to MSB).
Counter Modulus • Modulus of a counter is the number of states through which a counter progresses. • A Mod-12 UP Counter counts 12 states from 0000 (010) to 1011 (1110). The process then repeats. • A Mod-12 DOWN counter counts from 1011 (1110) to 0000 (010), then repeats.
State Diagram • A diagram that shows the progressive states of a sequential circuit. • The progression from one state to the next state is shown by an arrow. • (0000 0001 0010). • Each state progression is caused by a pulse on the clock to the sequential circuit.
MOD 12 Counter State Diagram • With each clock pulse the counter progresses by one state from its present position on the state diagram to the next state in the sequence. • This close system of counting and adding is known as modulo arithmetic.
Truncated Counters – 1 • An n-bit counter that counts the maximum modulus (2n) is called a full-sequence counter such as Mod 2, Mod 4, Mod 8, etc. • An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4).
Truncated Counters – 2 • A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter. • A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter.
Counter Timing Diagrams – 1 • Shows the timing relationships between the input clock and the outputs Q3, Q2, Q1, …Qn of a counter. • For a 4-bit mod 16 counter, the output Q0 changes for every clock pulse, Q1 changes on every two clock pulses, Q2 on four, and Q3 on 8 clocks.
Counter Timing Diagrams – 2 • The outputs (Q0 Q3) of the counter can be used as frequency dividers with Q0 = clock 2, Q1 = clock 4, Q2 = clock 8, and Q3 = clock 16. • The frequency is based on T of the output, not a transition on the output. • The same is true for a mod 12, except Q3 = clock 12.
Synchronous Counters • A counter whose flip-flops are all clocked by the same source and change state in synchronization. • The memory section keeps track of the present state. • The control section directs the counter to the next state using command and status lines.
Analysis of Synchronous Counters – 1 • Set equations for the (JK, D, T) inputs in terms of the Q outputs for the counter. • Set up a table similar to the one in Table 9.5 and place the first initial state in the present state column (usually all 000). • Use the initial state to fill in the Inputs that will cause this state on a clock pulse.
Analysis of Synchronous Counters – 2 • Determine the result on each FF in the counter and place this in the next state. • Enter the next state on the present state line 2 and repeat the process until you cycle back to the first initial state.
Present State Synchronous Inputs Next State 000 01 ( R ) 00 (NC) 11 ( T ) 001 001 01 ( R ) 11 (T) 11 ( T ) 010 010 01 ( R ) 00 (NC) 11 ( T ) 011 011 11 ( T ) 11 (T) 11 ( T ) 100 100 01 ( R ) 00 (NC) 01 ( R ) 000 State Table For Figure 9.11
Basic Design Approach – 1 • Draw a state diagram showing state changes and inputs and outputs. • Create a present/next state table. • List present states in binary order and next states based on the state diagram.
Basic Design Approach – 2 • Use FF Excitation Tables to determine FF (JK, D, T) inputs for each present next state transition. • Specify inputs equations for each input and simplify using Boolean reductions. • A VHDL design for counters is done more easily and is not as time consuming.
Basic Design Approach – 3 • The previous two slides describe the process for designing counters by deriving and simplifying Boolean equations for a counter (classical approach). • VHDL design for counters is done more easily and is not as time consuming.
VHDL Process Statements • Sequential counters use a process statement to control transitions to the next count state. • A VHDL Attribute is used with an identifier (signal) to define clock edges. • Clock uses an attribute called EVENT such as (clk’EVENT AND clk=‘1) to define a rising edge clock event.
VHDL UP Counter -- simple_int_counter.vhd -- 8-bit synchronous counter with asynchronous clear. -- Uses INTEGER type for counter output. LIBRARY ieee; USE ieee.std_logic_1164.ALL;
VHDL UP Counter Entity ENTITY simple_int_counter IS PORT( clock : IN STD_LOGIC; reset : IN_STD_LOGIC; q : OUT INTEGER RANGE 0 TO 255); END simple_int_counter;
VHDL UP Counter Architecture – 1 ARCHITECTURE counter OF simple_int_counter IS BEGIN PROCESS (clock, reset) VARIABLE count : INTEGER RANGE 0 to 255; BEGIN IF (reset = ‘0’) THEN COUNT : = 0;
VHDL UP Counter Architecture – 2 ELSE IF (clock’ EVENT AND clock = ‘1’) THEN count := count +1; END IF; END IF; q <= count; END PROCESS; END counter;
VHDL UP Counter Summary • PROCESS statement monitors the two inputs clock and reset, which controls the state of the counter. • A variable count holds the present value of the counter. • The IF statement evaluates the clock and reset inputs to determine whether the counter should increment or clear.
LPM Counters – 1 • The Altera LPM (Library of Parameterized Modules) counter can be used to create counter designs in VHDL. • This is a structured design approach that uses the LPM-counter as a component in a hierarchy. • The LPM counter is instantiated in the structured design.
LPM Counters – 2 • The basic parameters of the LPM counter, such as width, are defined with a generic map. • The port map is used to connect LPM counter I/O to the actual VHDL design entity.
VHDL LPM Library Declaration • The Altera LPM Library must be added to the usual STD_LOGIC after the ieee library has been declared LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL;
VHDL LPM Entity • Entity for an 8-bit mod 256 counter. LPM requires the use of STD_LOGIC data types. ENTITY simple_lpm_counter IS PORT( clk, clear : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 downto 0)); END simple_lpm_counter;
VHDL LPM Architecture ARCHITECTURE count OF simple_lpm_counter IS SIGNAL clrn : STD_LOGIC;--internal signal for active low clr. BEGIN -- Instantiate 8-bit counter. count : lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP (clock => clk, aclr => clrn,--Intrnal clear mapped to async. clr. q => q_out (7 downto 0 )); clrn <= not clear;--Input port inverted mapped to internal clr. END count;
Entering Simple LPM Counters in Quartus II • Use either the MegaWizard Plug in Manager or manually enter the LPM component. • Refer to Chapter 9, Entering Simple LPM Counters with the Quartus II Block Editor.
LPM Counter Features – 1 • Parallel Load: A function (syn/asyn) that allows loading of a binary value into the counter FF. • Clear: asynchronous or synchronous reset. • Preset: A set (syn. Or asyn.).
LPM Counter Features – 2 • Counter Enable: A control function that allows a counter to count the sequences or disable the count. • Bi-Directional: A control line to switch the counter from a count up to a count down.
LPM Counter Features – 3 • There are other features for LPM counters that are given in the Altera Reference Data Sheets. • The same holds true for other LPM functions, such as arithmetic and memory.
4-Bit Parallel Load Counter – 1 • A preset counter (parallel load) has an additional input (load) that can be synchronous or asynchronous and four parallel data inputs. • The load pulse selects whether the synchronous counter inputs are generated by count logic or parallel load data.
4-Bit Parallel Load Counter – 2 • An asynchronous load counter uses an asynchronous clear or preset to force the counter to a known state (usually 0000 or 1111).
Count Enable Logic • As shown in Figure 9.46, adding another AND gate to each FF input inhibits the count function. • This has the effect of inhibiting the clock to the counter (a clock pulse has no effect). • Outputs remain at the last state until the counter is enabled again.
Bi-Directional Counter • Adds a direction Input (DIR) to the counter and the control logic for up or down counting. • Basic counter element is shown in Figure 9.50. • The control logic selects the up or down count logic depending on the state of DIR.
Terminal Count Decoding – 1 • Uses a combinational decoder to detect when the last state of a counter is reached (terminal count). • Determines a maximum count out for an UP counter and a minimum for a DOWN counter.