1 / 8

Exploring Computer Architecture: A Deep Dive into ISA, Microarchitecture, and System Levels

This lecture outlines the key concepts of computer architecture, emphasizing trade-offs inherent in Instruction Set Architecture (ISA), microarchitecture, and system-level design. It covers vital topics like dynamic vs. static interfaces, fixed-length vs. variable-length instruction sets, load/store architectures, and the importance of compatibility and addressing modes. The session highlights two illustrative ISAs—LC-3b and x86—while delving into microarchitecture features such as CPI, branch prediction, and pipeline depth. Finally, it examines system-level considerations, including memory control and interconnection structures.

celestyn
Télécharger la présentation

Exploring Computer Architecture: A Deep Dive into ISA, Microarchitecture, and System Levels

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture 2: Computer Architecture: A Science ofTradeoffs

  2. Outline • The ISA • The Microarchitecture • The System level

  3. The ISA(visible to the software) • Dynamic/Static Interface • What at compile time, what at run time • Rich instruction set vs. simpler instruction set • Fixed-length, Uniform Decode vs. … • Condition codes vs. … • Load/Store vs. … • Help for the Programmer vs. help for the uarchitect • Addressing modes • Data types • Unaligned accesses

  4. The ISA (continued) • Hardware interlocks vs. … • VLIW vs. … • 0,1,2,3 address machine • Compatibility vs. a new ISA • Precise exceptions vs. … • Vectored interrupts vs Polling • Address space (16-bit  32-bit  64-bit)

  5. Two example ISAs • LC-3b (from EE 360n) • Load/store, 3-address machine • Few opcodes, addressing modes, data types • Fixed length, uniform decode • x86 • Not load/store, 2-address machine • Variable length, decoding nightmare • Prefixes • Many opcodes, addressing modes, data types • Dense encoding (comprehensive instructions) • Mod/RM, SIB, addressing mode offset, literal operand • Virtual memory PLUS segmentation • Memory-mapped PLUS I/O instructions

  6. The Microarchitecture(underneath the hood) • CPI vs. cycle time (or, IPC vs. frequency) • in-order vs. out-of-order execution • Speculate vs. stand around and wait • Issue-width • ASIC vs. programmed control • Use of chip real estate • Better branch predictor • Accelerators • Microcode • Pipeline depth • Cache structures

  7. Microarchitecture (continued) • Fault tolerance • Yesterday: Tandem (Two cores in lock step) • Tomorrow: repeat to remove errors (or 2 cores lockstep) • On-chip latency • near neighbor communication • Branch target buffer • saves a bubble on a taken branch • Partitioning – until when?

  8. The System • MP granularity (loosely coupled vs. tightly) • Distributed shared memory versus centralized • Interconnection structure • Use of commodity vs tailored parts • What do we integrate on chip • Memory controller • Analog devices

More Related