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From microelectronics down to nanotechnology

From microelectronics down to nanotechnology. sami.franssila@tkk.fi. Contents. Lithography: scaling x- and y-dimensions MOS transistor physics Scaling oxide thickness (z-dimension) CNT transistors Conducting wires (metals and CNTs) Memories Moore’s law and fabrication economics.

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From microelectronics down to nanotechnology

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  1. From microelectronics down to nanotechnology sami.franssila@tkk.fi

  2. Contents • Lithography: scaling x- and y-dimensions • MOS transistor physics • Scaling oxide thickness (z-dimension) • CNT transistors • Conducting wires (metals and CNTs) • Memories • Moore’s law and fabrication economics

  3. Top down nanotechnology Scaling from micrometer down • Production-proven techniques • Laboratory techniques • Laboratory tricks Issues to be tackled: • Cost • Area • Speed • Defect density

  4. Writing patterns By pen • easy to write anything • slow to write long works • easy to change your mind in the middle By printing press • very fast for large number of copies • expensive to make the first copy • expensive to make changes

  5. Pen vs. printing press • AFM needle • electron beam • optical projection • nanoimprint

  6. Lithography Printing press style: • optical: mainstream • EUV/X-ray: small linewidth but otherwise problematic • imprint: partial solution at the moment; only certain aspects proven Pen-like: • electron beam: slow writing speed • ion beam: very slow writing speed, ultimate resolution • AFM, dip-pen,...

  7. The goal of lithography is to make lines and spaces small (only this will increase device packing density)

  8. gap Contact/proximity lithography light from light source quartz mask with chromium pattern photoresist covered silicon wafer

  9. Resolution= line + space Resolution =3 ( /n)* (gap + ½ thickness ) •  (Hg-lamp line) 436 nm • gap between mask and resist g  5 µm • d resist thickness d  1 µm • n resist refractive index n  1.6 • 1 µm in production • 100 nm in research

  10. Sources of radiation (UV 365 nm-436 nm, DUV 193 nm-248 nm, EUV, X-rays, electrons, ions) Optical system I (lenses, mirrors) Mask (pattern) Optical system II (lenses, mirrors) Numerical aperture NA=sin  Imaging medium (resist) Wafer (with patterns) Wafer stage (alignment mechanism)  Projection lithography

  11. Resolution = k1/NADepth of focus = k2/NA2

  12. Resist trimming trick • Isotropically etch resist • thinner & narrower lines • line-to-line spacing unchanged Works best for narrow initial lines Used in industry

  13. binary mask (quartz/chrome) phase shift mask (PSM) shifter Phase shift masks (PSM) • Conditions for phase shifter: • = 2L/ • = 2nL/. • L(n-1) = /2 amplitude intensity resist exposure threshold

  14. quartz quartz quartz quartz quartz quartz quartz Phase Shift Mask Fabrication 2-resist way Single resist way

  15. PSM produces /2 lines !

  16. X-ray lithography • Contact/proximity lithography • = 13 nm, resolution very good • highly penetrating radiation • not sensitive to particles, but • need thick metal to block x-rays • need 1X original because no x-ray mirrors

  17. Optical vs. X-ray masks -reduction optics -mask is final size -flat structures -highly 3D structures 40 nm of metal stops UV light; Need >1 µm thick metal to stop X-rays

  18. Electron beam lithography (EBL) • beam spot size 5 nm easily • beam scattering in resist (in all solids) • 10 nm can be made, but not easily • use higher energy ( heating, charging) • use thinner resist ( etch resistance down, defects up)

  19. Spot size vs. linewidth • linewidth typically 3*spot size to ensure reproducibility and reduce roughness missing pixels

  20. Raster vs. vector scanning Pixel-by-pixel raster scan; exposure / no exposure decision at each pixel “Intelligent skipping of empty spaces”

  21. EBL pros and cons • flexible writing of structures individually • writing speed very low indeed  small areas only • better resolution lower writing speed • thinner resist better resolution, worse etch and implant resistance, danger of pin hole defects

  22. Nano imprint (NIL) • 1X master is pressed against polymer • force is used (pressure, temperature, UV) • release of the master • clearing the bottom residue • feature size limited by master fabrication only

  23. NIL results

  24. NIL problems Problem 1: • need 1X original pattern (cf. X-ray lithography) Problem 2: • need 3D original master Problem 3: • Lifetime of the master ? Does repeated contact with the polymer damage or contaminate the master ? Problem 4: • Who is the first one to try something really new which may not work in production ?

  25. field oxide gate polysilicon • gate oxide source channel drain gate length Lg MOS transistor The goal of silicon processing and thin film technology is to control diffusion depths, film thicknesses and interfaces at atomic precision.

  26. MOS gate oxide seem by TEM “Metal” gate made of highly doped polycrystalline silicon Amorphous oxide Single crystalline silicon substrate

  27. Scaling of gate oxide • Gate oxide thickness  gate length/50 Lg Tox • 1960’s 30 µm 600 nm • 1970’s 5 µm 200 nm • 1980’s 1 µm 20 nm • 1990’s 0.35 µm 7 nm • 2000’s 100 nm 2 nm

  28. Oxide thickness limitations • Leakage current (tunneling) • Pinhole defects • Trapped charge • Interface traps • Interface structure (dangling bonds) • Crystallization and grain boundaries (not in SiO2 !)

  29. Leakage current explodes below 2 nm

  30. High-k dielectrics (e.g. HfO2) Because most high dielectric constant materials (high-k) are oxides, some oxygen is present during deposition, and some SiO2 is formed at the interface. The question is: can you control its formation and thickness with Ångström accuracy ?

  31. EOT: Equivalent Oxide Thickness EOT = (SiO2/ high) * thigh-+ tSiO2 where tSiO2 is the interfacial silicon dioxide thickness, if any. ZrO2 film of 6 nm physical thickness with 23 has EOT  1 nm

  32. Control of oxide layer Gate First High-k/Metal Gate Stacks With Zero SiOx Interface Achieving EOT=0.59 nm for 16 nm Application, VLSI Technology Symposium 2009

  33. Half time

  34. CNT transistors

  35. Transistor characteristics

  36. CNT network transistors (TKK) Random network, many current paths from source to drain. High performance compared with polymer transistors

  37. CNTN transistors (TKK)

  38. CNT circuitry by IBM (2006) The five-stage CMOS type nanotube ring oscillator using palladium p-type gates and aluminum n-type gates. The upper right inset shows the nanotube itself with a diameter of ~2 nm.

  39. CNT transistor time scales • 1998 first CNT transistor (FET) • 2001 logic gate • 2002 Schottky switch • 2002 top gate FET • 2003 ballistic transport demonstrated • 2004 AC characterization • 2006 circuit demo, 72 MHz ring oscillator • 2015? commercial devices (IBM guess)

  40. Metallization 6 levels of metal, cross section IC complexity increase over time

  41. W T metal L H dielectric IC metal wire scaling (by n>1) C’ =  (W/n)L/(T/n) = C R’ =L/(H/n)(W/n) = n2R RC time delay ’ is then given by ’ = R’C’ = n2RC While transistor performance improves with downscaling, scaled metal wires are worse !

  42. Electromigration Momentum transfer and displacement of lattice atoms by electrons Depends on bond strength (which can be gauged by melting point) Aluminum, low melting point, 650oC, low electromigration resistance Copper 1083oC Tungsten 3387oC improved EM resistance Hu, C.-K. et al: Electromigration of Al(Cu) two-level structures: effect of Cu kinetics of damage formation, J.Appl.Phys. 74 (1993), p. 969

  43. Grain size effects in metals Mechanical properties scale beneficially with smaller grain size Thermal properties mostly unchanged Resistivity increases with decreasing grain size Erb et al: in The Nano-Micro Interface, Wiley-VCH 2004

  44. Resistivity depends on patterns! You cannot calculate thickness from resistance R = ρL/Wt because thin film resistivity ρ is linewidth and thickness dependent (use e.g. X-rays to get an independent thickness value) G.B. Alers, J. Sukamto, S. Park, G. Harm and J. Reid, Novellus Systems, San Jose -- Semiconductor International, 5/1/2006

  45. Grain size affected by: -underlying film (chemistry and texture) -deposition process (sputtering vs. plating; & plating A vs. plating B) -material purity -thermal treatments -geometry of structures on wafer G.B. Alers, J. Sukamto, S. Park, G. Harm and J. Reid, Novellus Systems, San Jose -- Semiconductor International, 5/1/2006

  46. Current density barrier Electromigration limit of metals ca. 1 MA/cm2

  47. Vertical CNT connections Seeded growth in contact holes

  48. CNT’s show ohmic behaviour at current density 4*108 A/cm2

  49. Flash memory: close to limits tunnel oxide 10 nm interpoly oxide/nitride/oxide 50 nm Gate linewidth 100 nm Limit: thinner tunnel oxide traps charge and does become leaky (10 000 to 100 000 rewrites)

  50. PCM: phase change memory Chalcogenide materials exhibit • 100X resistivity difference between crystalline and amorphous states • factor of 2 difference in reflectivity Memory programmed and read electrically and/or optically

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