Please see “ portrait orientation ” PowerPoint file for Appendix A

1. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.1. Light switch example.

5. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.5. Minimization using Karnaugh maps.

6. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.6. Four-variable Karnaugh maps illustrating don’t cares.

12. Figure A.12. A transistor circuit implementation of a NOR gate.

14. (a) NMOS transistor (b) PMOS transistor

15. (b) Truth table and transistor states Figure A.15. CMOS realization of a NOT gate.

17. (b) Truth table and transistor states (a) Circuit (b) Truth table and transistor states Figure A.17. CMOS realization of a NAND gate.

18. (a) Circuit (b) Truth table and transistor states Figure A.18. CMOS realization of a NOR gate.

19. Figure A.19. CMOS realization of an AND gate.

20. V f V Slope =  1 s u p p l y 0 V V  d V + d V t t s u p p l y V x V t Figure A.20. The voltage transfer characteristic for the CMOS inverter.

21. T ransition time V 10% 1 Input waveform 50% 90% V 0 Propagation delay V 1 90% Output waveform 50% V 10% 0 T ransition time Figure A.21. Definition of propagation delay and transition time.

22. e = 0 f x e x f e = 1 x f (a) Symbol (b) Equivalent circuit f e x e 0 0 Z 0 1 Z x f 1 0 0 1 1 1 (c) Truth table (d) Implementation Figure A.22. Tri-state buffer.

23. Figure A23.A 14-pin integrated circuit package (DIP).

25. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.25. Gated SR latch.

27. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.27. Gated D latch.

28. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.28.Master-slave D flip-flop.

29. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.29. A negative edge-triggered D flip-flop.

30. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.30. T flip-flop.

32. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.32. Master slave D flip-flop with Preset and Clear.

33. F F F F 1 2 3 4 In Out D Q D Q D Q D Q Clock Q Q Q Q Figure A.33. A simple shift register.

37. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.37. A BCD to seven-segment display decoder.

38. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.38. A four-input multiplexer.

40.       •••      

42. Please see “portrait orientation” PowerPoint file for Appendix A Figure A.42. A simplified sketch of the PLA in Figure A.41.

45. PAL-like PAL-like             PAL-like PAL-like Figure A.45. Structure of a complex programmable logic device (CPLD).

47. x = 0 ¤ z = 0 S0 S1 x = 1 ¤ z = 0 x = 1 ¤ z = 0 x = 0 ¤ z = 0 x = 0 ¤ z = 0 x = 1 ¤ z = 1 x = 1 ¤ z = 0 S3 S2 x = 0 ¤ z = 1 Figure A.47.State diagram of a mod-4 up/down counter that detects the count of 2.