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A Low-Power Low-Voltage 10-bit 100-MSample

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A Low-Power Low-Voltage 10-bit 100-MSample

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    1. A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques Kazutaka Honda, Student Member, IEEE, Masanori Furuta, Member, IEEE, and Shoji Kawahito, Senior Member, IEEE Adviser : Hwi-Ming Wang Student : Wei-Guo Zhang Date : 2009/7/14

    2. Outline ABSTRACT INTRODUCTION DESIGN OF KEY BUILDING BLOCKS MEASUREMENT RESULTS CONCLUSION REFERENCES

    3. Abstract This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter using capacitance coupling techniques A capacitance coupling sampleand-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology SNDR of 55.3dB ;SFDR of 71.5 dB power consumption is 33mW at 1.0V supply voltage

    4. Introduction High-performance ADC is one of the key analog building blocks in system-on-a-chip (SoC) visual and telecommunication To exploit advanced sub-100-nm CMOS technology optimized for digital systems, the ADC is desired to be designed with the same devices and supply voltage as those used for the digital system. As device feature size is scaled down, digital circuits benefit greatly from both speed and power dissipation. For analog circuits, however, the decrease of supply voltage consequently causes reduced signal swing and degraded performances in switches and amplifiers

    5. Introduction Pipeline architectures have been widely employed in applications requiring high speed and high resolution with relatively low power dissipation supply voltage of 1.2 v For lower-voltage operation,the switched opamp (SO) technique is proposed to overcome the switch driving problem caused by an insufficient gate-source voltage This technique tends to slow operation due to slow transients from the opamp being switched on and off. Moreover, to maintain the same signal-to-noise ratio (SNR) with a lower supply voltage, the thermal noise in the circuit must also be proportionately reduced .This means that the sampling capacitance must be increased to reduce KT/C noise.

    6. Introduction

    7. DESIGN OF KEY BUILDING BLOCKS

    8. DESIGN OF KEY BUILDING BLOCKS

    9. DESIGN OF KEY BUILDING BLOCKS

    10. DESIGN OF KEY BUILDING BLOCKS

    11. DESIGN OF KEY BUILDING BLOCKS This amplifier utilizes a dynamical-bias gain boosting technique to have sufficient signal swing and allows the output swing of 0.8 vpp in differential signal under a 1.0-V power supply

    12. DESIGN OF KEY BUILDING BLOCKS

    13. DESIGN OF KEY BUILDING BLOCKS

    14. DESIGN OF KEY BUILDING BLOCKS

    15. DESIGN OF KEY BUILDING BLOCKS

    16. MEASUREMENT RESULTS

    17. MEASUREMENT RESULTS

    18. MEASUREMENT RESULTS

    19. MEASUREMENT RESULTS

    20. MEASUREMENT RESULTS

    21. MEASUREMENT RESULTS

    22. Conclusion

    23. REFERENCES

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