Chapter 7

1. Chapter 7 Hardware Details of 68000

2. BASIC PIN DISTRIBUTATION • 64 Pins • Communicates with outside world with 16 bit bi-directional data-bus. • 24-bit address bus • Control Signals • 3 Interrupt Lines for Hardware Interrupt • Three Control output for interfacing peripherals • Clock speed of 4 to 16 MHz.

3. CPU PIN DESCRIPTION • Vcc, GND, CLK • Processor power and clock inputs • There are two pins for each Vcc and GND. • Roughly 300mA is required as supply current. • For clock rise and fall times are limited to 10nsec • The clock waveform must be a TTL compatible of 50% duty cycle. • Crystal oscillator is used for stable clock frequency.

4. FC0, FC1, FC2 • Encoded processor state. • Indicates the current internal processing state of 68000. • The function code outputs are only valid when the processor’s AS’ signal is active. • Prcessing states are divided into user data, user program, supervisor data, supervisor program, and interrupt acknowledge. • 74LS318 can be used as the decoder.

5. E, VMA, and VPA • To control the older 68000 peripherals. • These signals facilitates the designer to translate their design from 8-bit upto 16-bit designs. • E Clock is used for the proper timing signals for 6800 peripherals • It is derived from 68000 clock by dividing by 10 • Valid peripheral address input is used to inform the 68000 that it has the addressed a 6800 peripheral and the data transfer should be synchronized. • Valid Memory Access output indicates the above synchronization. • It goes low when processor synchronizes with E clock.

6. Synchronization Sequence • The 68000 output the address of a 6800 peripheral on A1 through A23. • The peripheral circuitry responds by pulling VPA low. • When synchronization is achieved it is indicated by pulling VMA low. • Then Data transfer takes place.

7. RESET HALT & BERR • Used for system Control. • BERR input is used to inform the processor that the cycle currently executing has a problem and it should take appropriate action. • Processor has addressed an illegal memory location. • Other kind of bus error has occurred. • The 68000 chose between • Performing bus error exception • Returning bus cycle • If HALT line is not asserted when the bus error occurs, the 68000 start bus error exception processing., terminating the currently failed cycle. • If the HALT line was asserted before or at the same time as the BERR signal, the 68000 will rerun the bus cycle. • It does this by terminating the cycle and placing the data and address bus in high-impedance state. • The 6800 the enters a “Do Nothing” state until there is activity on HALT. • When HALT line is deactivated the processor will rerun the previous cycle.

8. IPL0 IPL1 & IPL2 • This is used for Priority level of the Interrupt control • Level 7 has the highest priority • Level 0 has the lowest priority

9. BR, BG, and BGACK • Used for Bus Arbitration Control • The requesting device called the bus master requests use of the 68000’s busses by activating BR input. • The 68000 will respond to its request by taking BG output low indicating that it will release control of the busses at the end o the current cycle. • When another master wants to take control it asserts BGACK (Bus Acknowledge) • Steps must be taken care before asserting BGACK • BG must be active • AS must be inactive, to show that the processor is not using the bus • DTACK must be inactive, to show no external devices are using the bus • BGACK must be inactive to ensure that no other bus master is using the bus

10. AS, R/W, UDS, LDS & DTACK • Asynchronous Bus Control • Address Strobe: is used to indicate is valid memory address exists on the address bus. • Read/Write determines if the current cycle is read or write. • Upper/Lower Data Strobe is used to for transferring the 8-bit of data. • Data Transfer Acknowledge is used by external circuitry to perform asynchronous data transfer. • It is the job if the external hardware to activate or deactivate this signal at proper times.

11. SYSTEM TIMING DIAGRAMS