CoolRunner™-II Technology & Architecture

1. CoolRunner™-II Technology & Architecture

2. Introducing CoolRunner-II • 0.18 process technology • System voltage integration • Advanced design features • Multiple I/O standards and I/O banks • Input hysteresis • Extra clocking modes • Architecture allows design flexibility • Ultra low power using RealDigital technology • Allows CoolRunner full-CMOS circuitry to run at extremely low power without compromising performance

3. High Level Architecture Clock and Control Signals Function Block 1 Function Block n MC1 MC1 16 FB 16 FB I/O MC2 MC2 I/O I/O I/O PLA PLA 16 16 I/O Blocks I/O Blocks AIM 40 40 I/O I/O MC16 MC16 16 16 Direct Inputs Direct Inputs

4. Function Block • 16 macrocells available • 40 true and complement input signals from AIM • Global signals available at macrocell • Product terms add more clocks, OEs, S/Rs • Product term sharing allows very high fit rate • PLA architecture features excellent pinlocking

5. Function Block Architecture 40 From AIM MC 1 Feedback to AIM PLA Array 40x56 To I/O Block 16 56 Product Terms MC 16 3 Global Clocks Global Set/Reset

6. PTA CTS GSR GND = programmable cell = product term signals = control term set = control term reset = control term clock PTA,B,C CTS CTR CTC PTA CTR GSR GND Macrocell Architecture FB Inputsfrom AIM application notes: http://www.xilinx.com/apps/epld.htm 40 PLA Array 49 P terms Macrocell 4 Control Terms from I/O Block (Direct Input) Feedback to AIM PTA PTB VCC PTC GND to I/O S Q D/T FIF Latch DualEDGE 3 CE PTC GCK CK R CTC PTC

7. Weak Pullup/Bus Hold I/O Pin I/O Pin I/O Block Characteristics VREF for Local Bank HSTL & SSTL VCCIO VREF to AIM 128 macrocell and larger devices Input Hysteresis to Macrocell (Direct Input) 3.3V - 1.5V Input Slewrate VCCIO from Macrocell Enabled Control Term PTB / 4 GTS[0:3] CGND Open Drain Disabled

8. Icc = C x V x f + Iddq To reduce power: Lower capacitance Lower voltage Lower frequency 0.18 m lowers capacitance Low VCC @ 1.8V How can we reduce the frequency? Reducing Power ~ 200mA Traditional Sense Amp Designs 1.8 Volt (est) 2.5 Volt Icc 3.3 Volt ~ 100mA Frequency ~ 200MHz Note: 128 MC device estimate

9. Global Clock(GCK2) DIV2 to FB 1 Clock Divide By 2,4,6,…,16 DIV4 ExternalSyncReset to FB n DIV16 Divide Select Clock Division • Gives solid clock division without using macrocells • Duty cycle improvement • Available in larger densities (128 macrocells and above)

10. DualEDGE Flip Flops to I/O D/T/L Q Advantages: • Distribute divided clock globally then double locallyat macrocell • Decrease Icc on global clock nets • Use 2x clocking for double data rate (DDR) applications • No additional insertion delay D T FF Latch  DualEDGE 3 GCK PTC CE CLK CT PTC

11. CoolCLOCK Device Routing Input Clock Divide Macrocell MCClock Inputs D/T/L Q D T Latch  DualEDGE DIV2 GlobalDividedClock GCK2 Divide by 2 SyncReset

12. DataGATEAssertion Rail Configuration Bit Data Latch InputPin to AIM DataGATE • Available on all input pins (except JTAG pins) • Available for all I/O types • Selectable on a per pin basis • Data latch holds last valid pin value • DataGATE allows additional power savings • Can be used to disable active board inputs • DataGATE can be also used for debugging and Hot Plug Input

13. V CoolRunner-II _ In + 500mV Input Hysteresis • Supports simple oscillation schemes • Ideal for slow edge rate, noisy signals • Analog comparators & sensors • Hall effect switches • IR inputs • R/C oscillators • Eliminate external Schmitt trigger buffers • Reduces power consumption with slow signals

14. XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 1 1 2 2 4 4 I/O Banks LVTTL 33       LVCMOS 33, 25, 18, 15*     SSTL3_I, SSTL2_I, HSTL_I       Input Hysteresis Option       Slew Rate Control     CoolCLOCK     DataGATE       DualEDGE flip flop     Clock Divider       Bus Hold output       Hot Pluggable I/O Performance & Flexibility * 1.5V inputs need hysteresis

15. CoolRunner-II Applications • Ideal for high speed designs: • High performance CPLD • Advanced features • Voltage translation for “free” • Double data rates • Target device for portable designs: • Lowest power • Maximum battery life • Lower heat dissipation • Small packaging • Chip scale packaging

16. CoolRunner-II Family Overview speeds are preliminary and 1.5V inputs need hysteresis * Note: T P D

17. CPLD Software • CoolRunner-II Software support • ISE WebPACK 5.2i • WebFITTER • Full feature support • All Xilinx CPLDs supported! • CoolRunner-II • CoolRunner XPLA3 • XC9500/XL/XV • http://www.xilinx.com/ise

18. IQ Solutions • Multiple facets • Programmable products • IP cores • System solution boards • PLD family members available in the range of -40°C to +125 C : • Design services • eSP web portal • Customer education Device Type Spartan XL XC9500 & XL CoolRunner XPLA3 Spartan-II CoolRunner-II Spartan-IIE XCS05XL, XCS10XL, XCS20XL, XCS30XL, XCS40XL XC9536XL, XC9572XL XCR3032XL, XCR3064XL, XCR3128XL, XCR3256XL, XCR3384XL, XCR3512XL XC2S15, XC2S30, XC2S50, XC2S100, XC2S150, XC2S200 Q1CY03 Q1CY03

19. CoolRunner-II Technology Summary • Silicon performance of Xilinx FPGAs with the single-chip integration of CPLDs • Architecture combines 9500-style macrocell with XPLA3’s PLA for best silicon/software efficiency • Industry leadership in: • High performance • I/O standards • Clock management capability • Low-power features • Uncompromised performance at 1.8 volts

20. Appendix

21. Traditional CPLDs - bipolar sense amp product terms Always consumes power Even at standby Performance is traded for power consumption as devices get larger CoolRunner-II RealDigital design uses 100% CMOS for product terms Virtually no standby current Combines high performance & ultra low power No power limits on device size A B C D RealDigital : CMOS Everywhere - Zero Static Power RealDigital Design Advantage Turbo vs Non Turbo Larger R = slower response & less power Vcc A C B Sense amplifier 0.25mA each - Standby Higher ICC at Fmax

22. Logic Optimization PAL: Requires 4 pt’s! PLA: Requires only 3 pt’s! C A B C A B X = A & B # C Y = A & B # !C Can NOT share common logic Y X X Y Indicates ‘used’ junction Common logic may be shared in CoolRunner-II Indicates ‘unused’ junction Indicates ‘fixed’ junction

23. Address DDR SDRAM Data P Control DDR SDRAM Interface • DualEDGE facilitates DDR • Utilizes SSTL interface

24. 2.5V Flash 1.5V P 3.3V SRAM 1.8V I/O CoolRunner-II featuresflexible I/O banking System Voltage Integration

25. Flash CompactFlash Battery SRAM SMBus PDA IrDA LED P UART Docking Cradle LCD SPI Touchscreen Keypad

26. ADC LCD Panel Touch Screen Tablet ID SPI PWM High End Processor HIB Smart Battery SDRAM SMBus Compact Flash/ Expansion RF Module ISA Bus Web Tablet

27. Low Power Clock Divide • Input signals: global clock (GCK2) & external sync reset • Control bits: enable/disable, & delay bit • Divide by n (2, 4, 6, 8, 10, 12, 14, or 16) Clock Cycles 1st 3rd 5th 7th 9th 17th Global CLK2 Sync Reset Divide by 2 Delay bit = 0 (No delay) Divide by 16 Divide by 2 Delay bit = 1 (Delay enabled) Divide by 16

28. Clock Cycles 2nd 1st 3rd 4th 5th External CLK Internal Clock Doubler Without DualEDGE Din Output With DualEDGE Din Output DualEDGE Performance Twice the performance of the system clock with double data rate

29. ODD CLOCKS with DualEDGE and CLOCK Divider • Clock Divider gives ÷ 2,4,6,8,10,12,14,16 • Dual EDGE double response • ODD CLOCKS at DualEDGE Flip Flops • ÷ 7 ÷ 14 x 2 • ÷ 5 ÷ 10 x 2 • ÷ 3 ÷ 6 x 2

30. Multiple CLOCKS with One Global net • Example: • GCK2 @ pin ÷ 8 distributes to Global Net • Some flops accept CLOCK, respond to ÷ 8 • Some DualEDGE Flip Flops respond to ÷ 4