1 / 35

ETE 204 - Digital Electronics

ETE 204 - Digital Electronics. Latches and Flip-Flops. [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB. Brief introduction to. Sequential Logic Circuits. Summer 2012. ETE 204 - Digital Electronics. 2. Sequential Logic Circuits.

drake-ayers
Télécharger la présentation

ETE 204 - Digital Electronics

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ETE 204 - Digital Electronics Latches and Flip-Flops [Lecture:12] Instructor: Sajib Roy Lecturer, ETE, ULAB

  2. Brief introduction to Sequential Logic Circuits Summer 2012 ETE 204 - Digital Electronics 2

  3. Sequential Logic Circuits ● The output of a sequential logic circuit is dependentnot only on the present inputs, but also on the pastsequence of the inputs. ● A sequential logic circuit must “remember” the pasthistory of the inputs. ● It does this using basic memory elements. - Latches - Flip-Flops Summer 2012 ETE 204 - Digital Electronics 3

  4. Sequential Logic Circuits outputs inputs Combinational Logic Circuit Memory Summer 2012 ETE 204 - Digital Electronics 4

  5. Basic Memory Elements Summer 2012 ETE 204 - Digital Electronics 5

  6. Basic Memory Elements ● Latch - Clock input is level sensitive. - Output can change multiple times during a clock cycle. - Output changes while clock is active.● Flip-Flop - Clock input is edge sensitive. - Output can change only once during a clock cycle. - Output changes on clock transition. Summer 2012 ETE 204 - Digital Electronics 6

  7. Basic Memory Elements Both latches and flip-flops use feedback to achieve “memory”. Summer 2012 ETE 204 - Digital Electronics 7

  8. Feedback Circuit with 2 Stable States What is the problem with this circuit? Summer 2012 ETE 204 - Digital Electronics 8

  9. Latches Summer 2012 ETE 204 - Digital Electronics 9

  10. Set-Reset (SR) Latch ● A Set-Reset Latch has two inputs - Set (S) input - Reset (R) input ● It can be constructed from two cross-coupled NORgates or two cross-coupled NAND gates. ● It has three modes of operation - Set: Latch output set to 1 (Q+ = 1) – Reset: Latch output reset to 0 (Q+ = 0) - Store: Latch output does not change (Q+ = Q) Summer 2012 ETE 204 - Digital Electronics 10

  11. SR Latch: using NOR gates A B NOR 0 X X' 1 X 0 Feedback NOR gates Summer 2012 ETE 204 - Digital Electronics 11

  12. SR Latch: Set (S = 1, R = 0) A B NOR 0 X X' 1 X 0 1 0 P = Q' 1 0 Summer 2012 ETE 204 - Digital Electronics 12

  13. SR Latch: Reset (S = 0, R = 1) A B NOR 0 X X' 1 X 0 0 1 P = Q' 0 1 Summer 2012 ETE 204 - Digital Electronics 13

  14. SR Latch: Store (S = 0, R = 0) Initial Condition: P = 0, Q = 1 A B NOR 0 X X' 1 X 0 0 0 P = Q' 1 0 Summer 2012 ETE 204 - Digital Electronics 14

  15. SR Latch: Store (S = 0, R = 0) Initial Condition: P = 1, Q = 0 A B NOR 0 X X' 1 X 0 0 1 P = Q' 0 0 Summer 2012 ETE 204 - Digital Electronics 15

  16. SR Latch: Behavior Present Next value value S R Q Q+ 0 0 0 0 • If S = 1 (Set), Q+ = 1 0 00 1 1 10 0 • If R = 1 (Reset), Q+ = 0 0 1 1 0 • If S = R = 0, Q+ = Q (no change) 1 0 0 1 1 01 1 1 10 not • S = R = 1 is not allowed. 1 1 1 allowed Summer 2012 ETE 204 - Digital Electronics 16

  17. SR Latch: Improper Operation P ≠ Q′ Summer 2012 ETE 204 - Digital Electronics 17

  18. SR Latch: Symbol always complementary Q' S Q SR Latch R Q' Q Summer 2012 ETE 204 - Digital Electronics 18

  19. SR Latch: Timing Diagram store set store reset Q' Q  = propagation delay of the latch Summer 2012 ETE 204 - Digital Electronics 19

  20. SR Latch: Characteristic Equation Q = present state Q+ = next state Characteristic Equation: Q+ = S + R'.Q (S.R = 0) Summer 2012 ETE 204 - Digital Electronics 20

  21. SR Latch: using NAND gates A B NAND 0 X 1 1 X X' S' R' Q Q+ 1 1 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 0 1 1 1 0 0 0 not 0 0 1 allowed Summer 2012 ETE 204 - Digital Electronics 21

  22. Gated D Latch ● A Gated D Latch has two inputs - Gate (G) input - Data (D) input ● It can be constructed from an SR Latch andadditional logic gates. ● It has the following behavior - G = 1: D is passed to Q (Q+ = D) - G = 0: Q remains unchanged (Q+ = Q)● Also referred to as a transparent latch. Summer 2012 ETE 204 - Digital Electronics 22

  23. Gated D Latch: Circuit and Timing NOR gates 23 Summer 2012 ETE 204 - Digital Electronics

  24. Gated D Latch: Symbol and Truth Table No invalid inputs! Summer 2012 ETE 204 - Digital Electronics 24

  25. Gated D Latch: Characteristic Equation 0 2 6 4 1 3 7 5 Characteristic Equation: Q+ = G'.Q + G.D Spring 2011 Summer 2012 ECE 30 - Digital Electronics ETE 204 - Digital Electronics 25

  26. Gated D Latch: using NAND gates S' R' NAND gates Summer 2012 ETE 204 - Digital Electronics 26

  27. Flip-Flops Summer 2012 ETE 204 - Digital Electronics 27

  28. D Flip-Flop ● A D Flip-Flop has two inputs - Clock (Ck) --- denoted by the small arrowhead - Data (D) ● The output of the D Flip-Flop changes in response tothe clock input only. - not in response to a change in the D input ● The D Flip-Flop is edge-triggered not level-sensitive - Positive (or rising) edge-triggered: 0 → 1 – Negative (or falling) edge-triggered: 1 → 0 Summer 2012 ETE 204 - Digital Electronics 28

  29. D Flip-Flop Characteristic Equation: Q+ = D 29 Summer 2012 ETE 204 - Digital Electronics

  30. D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? Summer 2012 ETE 204 - Digital Electronics 30

  31. D Flip-Flop (master-slave) Gated D Latches Enabled on opposite levels of the clock Summer 2012 ETE 204 - Digital Electronics 31

  32. D Flip-Flop: Timing Diagram Which clock edge is the D flip-flop triggered on? Summer 2012 ETE 204 - Digital Electronics 32

  33. D Flip-Flop: Setup and Hold Times Setup time Hold time Propagation delay Summer 2012 ETE 204 - Digital Electronics 33

  34. D Flip-Flop: Minimum Clock Period 34 Summer 2012 ETE 204 - Digital Electronics

  35. Questions? Summer 2012 ETE 204 - Digital Electronics 35

More Related