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Dual-Voltage Supply for Power Reduction

Dual-Voltage Supply for Power Reduction. ELEC 6970 – Low Power Design Project Presentation by Muthubalaji Ramkumar. Problem Statement.

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Dual-Voltage Supply for Power Reduction

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  1. Dual-Voltage Supply for Power Reduction ELEC 6970 – Low Power Design Project Presentation by Muthubalaji Ramkumar ELEC 6970 - Project Presentation

  2. Problem Statement To Use a dual-supply voltage in order to reduce the power consumption of the 32 x 32 bit integer array multiplier circuit without compromising the overall delay ELEC 6970 - Project Presentation

  3. Power and Delay Power → VDD2 Delay → KVDD ─────── (VDD – Vt)α ELEC 6970 - Project Presentation

  4. Approach • Low Voltage Assignment to as many cells as possible • The interconnections in this multiplier circuit makes it difficult • Therefore assign Low Voltage Supply to as many gates as possible ELEC 6970 - Project Presentation

  5. Things to watch • Reducing the Voltage Supply will increase the delay of a gate • Therefore assign Low-Voltage Supply only to the gates which do not have any influence on the Critical Path Delay directly or indirectly • Low voltage gate should have adequate voltage swing in order to drive a High Voltage gate its feeding in to. ELEC 6970 - Project Presentation

  6. Sum input B B3 B2 B1 B0 0 0 0 0 A A0 0 Y0 A1 0 Y1 Carry out Carry in A2 Full adder 0 Y2 A3 0 Y7 Y6 Y5 Y3 Y4 Sum output Cell Array 4 x 4 Multiplier ELEC 6970 - Project Presentation

  7. Multiplier Cell ELEC 6970 - Project Presentation

  8. Low-Voltage Supply Assignment ELEC 6970 - Project Presentation

  9. Total Number of gates = 6N2 • Number of gates with Low Voltage assignment = (N-1)(N+6) • Percentage of the circuit with Reduced VDD = (N-1)(N+6) / 6N2 ELEC 6970 - Project Presentation

  10. Percentage of the Circuit with Reduced Voltage Supply ELEC 6970 - Project Presentation

  11. Experimental Results for a Cell ELEC 6970 - Project Presentation

  12. Experimental Results for a 4 x 4 Multiplier ELEC 6970 - Project Presentation

  13. A Single Inverter ELEC 6970 - Project Presentation

  14. 4 x 4 bit array Multiplier • N=4 • Total Number of Gates = 6N2 = 6(16) = 96 • Number of Gates with Low VDD = (N-1)(N+6) = (3)(10) = 30 = 31.25 % • Number of Gates with Normal VDD = 96 – 30 = 66 = 68.75% ELEC 6970 - Project Presentation

  15. Power Estimation • Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.3125)(132.1uW) + (0.6875)(213uW) = 187.73 uW • 12% Power Reduction ELEC 6970 - Project Presentation

  16. Power Estimation • Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.3125)(75.8uW) + (0.6875)(213uW) = 170.125 uW • 20.13 % Power Reduction ELEC 6970 - Project Presentation

  17. 32 x 32 bit array Multiplier • N=32 • Total Number of Gates = 6N2 = 6(1024) = 6144 • Number of Gates with Low VDD = (N-1)(N+6) = (31)(38) = 1178 = 19.2 % • Number of Gates with Normal VDD = 6144 – 1178 = 4966 = 80.8% ELEC 6970 - Project Presentation

  18. Power Estimation • Using Dual-Voltages, 1.8V & 1.5V Power Consumption = (0.192)(8.45mW) + (0.808)(13.63mW) = 12.64 mW • 7.3% Power Reduction ELEC 6970 - Project Presentation

  19. Power Estimation • Using Dual-Voltages, 1.8V & 1.2V Power Consumption = (0.192)(4.85mW) + (0.808)(13.63mW) = 11.9 mW • 12.4% Power Reduction ELEC 6970 - Project Presentation

  20. Conclusion Pros… • Reduction in power • Delay is not compromised • No change in Area • Dual-power supply is easy to generate using potential dividers Cons… • The percentage of the circuit that can be fed with Low Voltage supply is less • Requires careful assignment of Low Voltage Supply ELEC 6970 - Project Presentation

  21. Comments • Learnt VHDL basics • Introduction to very useful EDA tools • Get a feel of VLSI Design • Appreciation of Low Power Design • Time Consuming but worth it ELEC 6970 - Project Presentation

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