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Introduction to Digital Systems Design: State Reduction Techniques

This course delves into the principles of digital systems design, focusing on state reduction for finite state machines (FSMs). By minimizing the number of states through analysis of state tables and transition diagrams, designers can achieve reduced complexity and cost, leading to fewer flip-flops and gates. The course covers essential techniques such as row matching for identifying equivalent states, along with various state assignment encoding methods. Key examples, including an odd parity checker, illustrate the application of these concepts in designing efficient digital circuits.

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Introduction to Digital Systems Design: State Reduction Techniques

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  1. ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Dr. Shi Dept. of Electrical and Computer Engineering

  2. STATE REDUCTION

  3. Overview • Important to minimize the size of digital circuitry • Analysis of state machines leads to a state table (or diagram) • In many cases reducing the number of states reduces the number of gates and flops • This is not true 100% of the time • In this course we attempt state reduction by examining the state table • Other, more advanced approaches, possible • Reducing the number of states generally reduces complexity.

  4. State Reduction: Motivation: lower cost fewer flip-flops in one-hot implementations possibly fewer flip-flops in encoded implementations more don’t cares in next state logic fewer gates in next state logic Simpler to design with extra states then reduce later. Example: Odd parity checker FSM Optimization

  5. “Row Matching” is based on the state-transition table: If two states have the same output and both transition to the same next state and self-loop or both transition to each other then they are equivalent. Combine the equivalent states into a new renamed state. Repeat until no more states are combined State Transition Table NS output PS x=0 x=1 S0 S0 S1 0 S1 S1 S2 1 S2 S2 S1 0 State Reduction

  6. Merge state S2 into S0 Eliminate S2 New state machine shows same I/O behavior Example: Odd parity checker. State Transition Table NS output PS x=0 x=1 S0 S0 S1 0 S1 S1 S0 1 FSM Optimization

  7. State Transition Table NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f g f 0 1 g a f 0 1 Row Matching Example

  8. NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e f 0 1 e a f 0 1 f e f 0 1 NS output PS x=0 x=1 x=0 x=1 a a b 0 0 b c d 0 0 c a d 0 0 d e d 0 1 e a d 0 1 Row Matching Example Reduced State Transition Diagram

  9. State Transition Table NS output PS x=0 x=1 a b c 1 b d f 1 c f e 0 d b g 1 e f c 0 f e d 0 g f g 0 Partitioning Minimization (Moore) • Step 1: P1= (abcdefg) • Step 2: P2=(abd)(cefg) • Step 3: • (abd) 0-successors (bdb) • (abd) 1-successors (cfg) • (cefg) 0-successors (ffef) • (cefg) 1-successors (ecdg) • P3: (abd)(ceg)(f)

  10. State Transition Table NS output PS x=0 x=1 a b c 1 b d f 1 c f e 0 d b g 1 e f c 0 f e d 0 g f g 0 Partitioning Minimization • Step 3: P3: (abd)(ceg)(f) • Step 4: • (abd) 0-successors (bdb) • (abd) 1-successors (cfg) •  b must be removed • (ceg) 0-successors (fff) • (ceg) 1-successors (ecg) • P4: (ad)(b)(ceg)(f)

  11. State Transition Table NS output PS x=0 x=1 a b c 1 b a f 1 c f c 0 f c a 0 Partitioning Minimization • Step 4: P4: (ad)(b)(ceg)(f) • Step 5: (verify no change)

  12. STATE ASSIGNMENT

  13. Encoding State Variables • Option 1: Binary values • 000, 001, 010, 011, 100 … • Option 2: Gray code • 000, 001, 011, 010, 110 … • Option 3: One hot encoding • One bit for every state • Only one bit is a one at a given time • For a 5-state machine • 00001, 00010, 00100, 01000, 10000

  14. Summary • Important to create smallest possible FSMs • This course: use visual inspection method • Often possible to reduce logic and flip flops • State encoding is important • One-hot coding is popular for flip flop intensive designs.

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