PIDS Roster

1. PIDS Preliminary Results and Key Issues: 2005 ITRSPeter M. Zeitzoff for PIDS Technology Working GroupITRS Public MeetingSan FranciscoJuly 13, 2005

2. PIDS Roster • Japan • T. Sugii (Chair) • S. Sawada • J. Ida • S. Oda • T. Hiramoto • S. Takagi • K. Shibahara • A. Hori • D. Hisamoto • T. Nakamura • Y. Tadaki • N. Nagashima • Y. Takeda • S. Tahara • K. Imai • Y. Akasaka • R. Shirota • M. Yoshimi • T. Sasaki • Taiwan • R. Liu (Chair) • Y. J. Mii • C. Diaz • W. T. Shiau • M. J. Tsai • Korea • I. S. Yeo • Europe • T. Skotnicki (Chair) • K. Schruefer • S DeLeonibus • K. De Meyer • R. Lander • M. Jurczak • US • P. Zeitzoff (Chair) • J. Chung • J. Brewer • L. Tran • M. Rodder • Q. Xiang • T-J. King • T. Ning • G. Yeap • M. Duane • T. Dellin • W. Tsai

3. Scope and Subcategories Non-Volatile Memory DRAM Logic Reliability Outline

4. PIDS = Process Integration, Devices, and Structures Main concerns MOSFET, memory, and passive devices and structures Device physical and electrical characteristics and requirements Broad issues of device and circuit performance, density, and power dissipation, particularly as they drive overall technology requirements Reliability PIDS Scope

5. Logic High-performance Low-power for mobile applications Memory DRAM Non-volatile memory (NVM) Reliability PIDS Subcategories

6. Scope and Subcategories Non-Volatile Memory DRAM Logic Reliability Outline

7. NOR Flash Technology node (F = minimum poly half pitch) remains unchanged from 2004 update. Tunnel oxide scaling slightly faster in near term. Interpoly EOT scaling faster in both near term and long term (deployment of high-k). Control gate Lg scaling is considerably faster than 2004 update. Cell size scaling is faster than 2004 update in both μm2 and F2. Advances result from good engineering, not fundamental breakthroughs. NAND Flash F moves past DRAM in both near term and long term. Cell size area factor, a = cell size/F2 remains the same (but F moves with node). W/E voltages remain the same as 2004 update (not moving with node). Tunnel oxide thickness remains the same as 2004 update. Interpoly dielectric thickness remains the same as 2004 update. Endurance and retention remain the same as 2004 update. Non-Volatile Memory (NVM) Preliminary Results

8. Technology Node(nm) Near-term Long-term Proposal of NAND/AND Flash Roadmap Preliminary Results

9. FeRAM Technology node still lags substantially behind DRAM/NAND Flash Ferroelectric capacitor area scaling slows down – 3D is major challenge Endurance improvement slows down starting from 2004. SONOS/NROM 2-bit/cell due to localized charge storage. Scalability expected similar to floating gate device. No floating gate coupling issues. MRAM Technology node pulls back by 1-2 years in near term and long term. Both switching field and switching energy are aggressively scaled after 2008 compared to 2004 update. Much of this acceleration is labeled “red” indicating breakthroughs are needed for MRAM to stay competitive. PCRAM New in 2005 PIDS: mainstream production expected soon. For near term years, technology node similar to DRAM. Non-Volatile Memory (NVM) (con’t.) Preliminary Results

10. Scope and Subcategories Non-Volatile Memory DRAM Logic Reliability Outline

11. Scaling unchanged from 2003 DRAM half-pitch (F) : 3 year cycle 65nm in 2007, 45 nm in 2010 Other results a=(cell area)/F2: a=8 through 2007, a=6 thereafter Area size factor (% of chip area taken up by storage cells): 63% through 2007, 56% thereafter STC storage node dielectric: the same as 2003 ITRS DRAM Preliminary Results

12. Potential Solutions: DRAM Preliminary Results

13. Scaling of DRAM Storage Dielectric Preliminary Results

14. Scope and Subcategories Non-Volatile Memory DRAM Logic Reliability Outline

15. MASTAR (detailed analytic device model from STM and corporate partners) was used MASTAR has been extensively verified against literature and other data Initial choice of scaled MOSFET parameters is made Using MASTAR, MOSFET parameters are iteratively varied to meet ITRS targets Types of Logic High Performance (HP) (e.g., MPU): target is historical 17%/year transistor performance increase Low Power (for mobile applications): target is specific, low level of leakage current Low Standby Power (LSTP): very low leakage; for lower performance, consumer applications (e.g., cellphone) Low Operating Power (LOP): low dynamic power, rel. high performance (e.g., notebook computer) 2005 scaling results changed somewhat from 2003 ITRS Logic: 2005 Scaling Approach and Categories

16. 2005 ITRS: Low Power & High Performance (HP) Intrinsic Transistor Delay, t = CV/I (lower delay = higher speed) Leakage Current (HP: standby power dissipation issues) HP LOP LSTP LOP LSTP Target: Isd,leak ~ 10 pA/um HP Target: 17%/yr, historical rate Preliminary Results

17. First Year of “Volume Production” 2020 2015 2010 2005 2000 HP LP Strained Si High k Gate Dielectric HP LP Metal Gate Electrode LP HP LP HP Fully Depleted SOI HP LP Multiple Gate MOSFET = Low Power Applications = High Performance Applications LP HP Driver: The “CMOS Change Crunch” Multiple, Big Changes Over Next 7 Years Others Preliminary Results

18. LSTP: EOT and Gate Leakage Current Density (Jg) Scaling Jg,sim (SiON) EOT Jg,limit Preliminary Results

19. Parallel Paths for High-Performance Logic in 2005 ITRS [MG = Multiple Gate (e.g., FinFET)] [FDSOI = Fully Depleted, Ultra-thin Body SOI] • Approach • Extend planar bulk as long as possible • Implement FDSOI in parallel with planar bulk • Establish MG later; MG is the ultimate, scaled CMOS Preliminary Results

20. Scope and Subcategories Non-Volatile Memory DRAM Logic Reliability Outline

21. High-k Gate Dielectrics Dielectric breakdown; Transistor instability Metal Gate Ion drift, VTH stability, oxidation; thermal-mechanical Cu/ Low k Electromigration and voiding; stability of interfaces; TDDB Impact of porous, weaker, less thermally conductive dielectrics Packaging Solder bumps; fracture; EM in packaging; CTE mismatch Design & Test for Reliability Reliability simulation; Reliability screens Reliability: Top 5 Near-Term Challenges Preliminary Results

22. Reliability risk is growing New materials (e.g., high k/metal gate; low k) and new devices (e.g., FINFET) and new packaging Introduce new and/or modified failure mechanisms Mechanisms need to be identified, modeled and controlled Have less-than-historic time and resources to ensure reliability Difficult tradeoffs may require reduced reliability margins Need new Design for Reliability tools and reliability screens Need to sustain current high reliability levels in spite of unprecedented changes Reliability: Key 2005 Issues Preliminary Results

23. Memory DRAM: Rapid scaling continuing Numerous different types of NVM, with unique attributes and scaling scenarios Logic High-performance logic: performance increases by 17%/yr. ratehigh leakage current Low-power logic: low leakage currentreduced performance Numerous and rapid technology innovations required 2005 ITRS: re-evaluation of scaling scenarios, timing and sequence of technology innovations Reliability Ensuring reliability for numerous and rapid technological innovations is a critical challenge Nevertheless, need to sustain current high reliability levels Summary

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25. Parallel Paths for LSTP in 2005 ITRS [FDSOI = Fully Depleted, Ultra-thin Body SOI] [MG = Multiple Gate (e.g., FinFET)] • Approach • Extend planar bulk as long as possible • Implement FDSOI and MG in parallel • Slowed Lg scaling for FDSOI in latter years Preliminary Results

26. Parallel Paths for LOP in 2005 ITRS [FDSOI = Fully Depleted, Ultra-thin Body SOI] [MG = Multiple Gate (e.g., FinFET)] • Approach • Extend planar bulk as long as possible • Implement FDSOI and MG in parallel • FDSOI ends in 2016 Preliminary Results