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PIDS Summary

ITWG Meeting Tokyo, Japan November 30 - December 1, 2004. Peter M. Zeitzoff US Chair. PIDS Summary. PIDS Summary. Logic With Design: need to further explore leakage and performance requirements Relation between gate and S/D leakage

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PIDS Summary

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  1. ITWG Meeting Tokyo, Japan November 30 - December 1, 2004 Peter M. Zeitzoff US Chair PIDS Summary

  2. PIDS Summary • Logic • With Design: need to further explore leakage and performance requirements • Relation between gate and S/D leakage • Re-evaluate LOP and LSTP performance vs. leakage requirements • Consider alternate, parallel scenarios for introduction of non-classical CMOS options in our scaling/technology requirements table for high-performance logic • Extending planar bulk until multiple-gate MOSFET is available vs. current option of introducing UTB FDSOI in 2008, then introducing multiple gate in 2010 • The reason to do this: better reflect reality • A “test case” for doing this using 2003 PIDS high-performance logic has been carried out • Tentative: main impact of extending bulk: increased leakage current, increased mobility enhancement factor from strain, mobility enhancement

  3. PIDS Summary • DRAM: no change in scaling of half pitch (F) from 2003 ITRSF=90nm in 2004 • Definition of F is bitline (M1) half-pitch • Survey sent out to main vendors, most of vendors have replied • Important issue: a=(storage cell area)/F^2. Currently is 8 for most vendors, when will it be reduced to 6? • Flash:preliminary surveyacceleration of scaling (for NAND/AND) by one year compared to DRAM

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