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PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting

PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting. Jim Hutchby - Facilitating Room: Mont Blanc 2 Atria Novotel - Grenoble, France 8:00 a.m - 4:00 p.m. April 25, 2001. PIDS ITWG Novel Devices Working Group Participants. George Bourinaoff Intel/SRC

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PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting

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  1. PIDS ITWG MeetingPIDS ITWGEmerging Research Devices Working Group Face-to-Face Meeting Jim Hutchby - Facilitating Room: Mont Blanc 2 Atria Novotel - Grenoble, France 8:00 a.m - 4:00 p.m. April 25, 2001

  2. PIDS ITWG Novel Devices Working GroupParticipants • George Bourinaoff Intel/SRC • Joop Bruines Philips • Joe Brewer U. Florida • Jim Chung Compaq • Peng Fang AMAT • Steve Hillenius Agere • Toshiro Hiramoto Tokyo U. • Jim Hutchby SRC • Dae Gwan Kang Hyundai • Makoto Yoshimi Toshiba • Kentarou Shibahara Hiroshima U. • Kristin De Meyer IMEC • Tak Ning IBM • Byong Gook Park Seoul N. U. • Luan Tran Micron • Bin Zhao Conexant • Victor Zhirnov SRC/NCSU • Ramon Compano Europe Com

  3. Prepare a sub-section of the 2001PIDS ITRS Assess advanced non-bulk CMOS-related technologies Assess potential and issues related to novel devices and technologies related to: Logic Memory Information Processing Architectures PIDS ITWG Emerging Devices Working GroupWorking Group Objectives

  4. Complete the Emerging Research Devices Tables Non Bulk CMOS Research Memory Devices Logic Devices Technologies Architectures Complete design and layout of the Emerging Technology Sequence Chart Set Working Group Agenda for completing our section Emerging Technology Sequence Chart (July ITRS Mtg.) Text descriptions of Table Entries (July ITRS Mtg.) Reference text for Table Entries (July ITRS Mtg.) Completed Emerging Research Devices Section (8/30) PIDS ITWG Emerging Devices Working GroupMeeting Objectives & Desired Outcomes

  5. 8:00Introductions 8:15 Review meeting objectives and agenda Hutchby 8:30 Review status of Emerging Research Hutchby Devices Section Tables (technology entries & row metrics) Identify points of consensus Identify issues not having consensus Emerging Technology Sequence Chart 9:00 Discuss Tables 9:00 Non-Bulk CMOS Table Yoshima 9:45 Memory Table Zhirnov 10:00 Break 10:15 Memory Table (continued) Zhirnov 11:00 Logic Table Compano 12:00 Lunch 1:00 Technology Table Hutchby 2:00 Architecture Table Bourianoff 3:00 Emerging Technology Sequence Chart Hutchby 4:00 Adjourn Meeting PIDS ITWG Emerging Devices Working GroupAgenda

  6. Model Table for Non-Bulk CMOS DevicesPIDS ITWG Emerging Research Devices Working Group

  7. Emerging Research Logic Devices1 PIDS ITWG Emerging earch Devices Working Group 1The time horizon for entries increases from left to right in these tables

  8. Model Table for Emerging Technologies1 PIDS ITWG Novel Devices Working Group 1The time horizon for entries increases from left to right in these tables

  9. Emerging Research Architectures PIDS ITWG Emerging Research Devices Working Group

  10. Bulk CMOS Nanotube PD SOI CMOS Self-assembly Technology Progression Technology features (add-on’s) High k gate dielectric Cu interconnect Low-k ILD Nanometer-scale CMP Metal gate Molecular devices 3D, heterogeneous integration High mobility (strained Si on SiGe) Wafer bonding & layer transfer Molecular devices Nanotechnology Air bridge Contacts to nanodevices Double-Gate CMOS Interconnects for nanodevices Feature Size: 100 nm 15 nm 2 nm Time

  11. Bulk CMOS Nanotube PD SOI CMOS Emerging Technology Sequence11This chart is intended to guide research. It is not intended to predict future technologies Architecture 3D-integration CNN & QCA networks Interconnects for nanodevices Wafer bonding & layer transfer Contacts to nanodevices Nanometer-scale CMP High k gatedielectric Technology Air bridge Self-assembly Cu interconnect Low-k ILD Metal gate Devices High mobility (strained Si / SiGe) Double-Gate CMOS Molecular devices Critical Size 100 nm 50nm 15nm 2nm Year 2005 2010 2020

  12. Should we have an entry for Fully Depleted SOI or just a single entry for SOI without specifying PD or FD. We are all agreed that we should have some kind of entry for SOI. The question is whether the entry should refer to SOI or to FD-SOI? Double gate structures. The Japan Region proposes to discuss 1) Vertical MOSFET, 2) DELTA, 3) double-gate MOSFET separately. NDWG IssuesNon Bulk CMOS Devices

  13. Novel Logic Devices. Should we refer to this table as the “Emerging Logic Devices Table”? Other tables could be similarly named, e.g., “Emerging Memory Devices Table”, etc. What position should we take regarding application of the NDWG’s judgement on the various entries? Should we leave any out if we think they are too speculative? Added Row Metric. The US Group added a new row metric entitled “Maturity”. This metric is proposed to be added to all the tables NDWG IssuesEmerging Logic Devices

  14. Given our position on the RTD and its lack of potential, due to its being a 2-terminal device, what position should we take on the newer versions of 2-terminal devices, such as molecular switches, consisting of single molecules operating in a tunneling mode? We all agree that we should have an entry for single molecular devices and for Carbon Nanotubes. Also, the Far East Region view is that we should keep the sub-category for RTD 2-terminal devices. The US Region agrees that we should keep the entry for the RTD 2-terminal device in the RTD-FET section. NDWG IssuesEmerging Logic Devices

  15. MRAM. Should we separate the entries for GMR and Tunnel Junction Devices? MRAM. The title “Pseudo-Spin-Valve Memory” might be substituted for “GMR Memory”. NDWG IssuesEmerging Memory Devices

  16. We need more discussion of how best to group these different memory types, and how best to categorize them with descriptive titles. Cell size, access time, retention time, write cycles and power. Should the “Yano Device” be a separate entry to the Memory Table? Crested Tunnel Barrier Memory. A concern is this title is specific to Prof. Liharev’s approach. Several other names including Nano Floating Gate have been suggested. Coulomb Blockade Memory. Concern has been expressed that this title is not descriptive. Another title of “Single Electron Memory” has been suggested. NDWG IssuesEmerging Memory Devices

  17. We need to decide whether and where to put 3-D Heterogeneous Integration? Specifically, do we put the 3-D Heterogeneous Integration in the Emerging Architecture Table? The US Region agrees this should be in the Emerging Architectures Table. We need to decide whether or not to keep the entries for Defect Tolerant Architecture and Molecular Computing in the Emerging Architecture Table? NDWG IssuesEmerging Architectures

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