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ERD ITWG Emerging Research Devices Working Group Face-to-Face Meeting

ERD ITWG Emerging Research Devices Working Group Face-to-Face Meeting. Jim Hutchby - Facilitating Grand Hotel Steigenburger Petersberg Rheinblick Room Koenigswinter (near Bonn), Germany Wednesday April 2, 2008 8:00 a.m. – 6:00 p.m.

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ERD ITWG Emerging Research Devices Working Group Face-to-Face Meeting

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  1. ERD ITWGEmerging Research DevicesWorking GroupFace-to-Face Meeting Jim Hutchby - Facilitating Grand Hotel Steigenburger Petersberg Rheinblick Room Koenigswinter (near Bonn), Germany Wednesday April 2, 2008 8:00 a.m. – 6:00 p.m

  2. ERD ITWGEmerging Research DevicesWorking GroupFace-to-Face MeetingMEMORY DISCUSSION Victor Zhirnov and Rainer Waser - Facilitating Grand Hotel Steigenburger Petersberg Rheinblick Room Koenigswinter (near Bonn), Germany Wednesday April 2, 2008 8:00 a.m. – 1:30 p.m

  3. To develop quantitative estimates of performance for the various types of memories We need to discuss and agree on the methodology we use and the numbers we obtained It is highly desirable to document the results, ideally as a journal publication To discuss new possible memory candidates Objectives

  4. 8:00 Review meeting objectives and agenda Hutchby 8:15 Introductory remarks on Memory Discussion Zhirnov 8:30 Nanowire Phase-change memory Meyyapan 9:30 Magnetic Race-Track & Spin-torque Transfer Memories Zhirnov 10:30 Break 10:45 Quantitative estimates of performance for the various types of memories Engineered barrier Muralidhar & Zhirnov Ferroelectric Waser Nanoelectromechanical Zhirnov Fuse/Antifuse Waser & Akinaga 12:00 Lunch 12:30 Continue quantitative estimates ….. Ionic Waser & Akinaga Electronic Effects Waser Macromolecular Zhirnov Molecular Waser 1:30 Break - Adjourn Memory Discussion 2:00 ERD Business Meeting ERD ITWG Memory DiscussionAgenda

  5. Emerging Research Devices Working Group • Hiroyugi Akinaga AIST • Tetsuya Asai Hokkaido U. • Yuji Awano Fujitsu • George Bourianoff Intel • Michel Brillouet CEA/LETI • Joe Brewer U. Florida • John Carruthers PSU • Ralph Cavin SRC • U-In Chung Samsung • Philippe Coronel ST Me • Shamik Das Mitre • Erik DeBenedictis SNL • Simon Deleonibus LETI • Kristin De Meyer IMEC • Michael Frank AMD • Christian Gamrat CEA • Mike Garner Intel • Dan Hammerstrom PSU • Wilfried Haensch IBM • Shigenori Hayashi Matsushita • Dan Herr IBM • Toshiro Hiramoto U. Tokyo • Matsuo Hidaka ISTEK • Jim Hutchby SRC • Yasuo Inoue Renesas Tech • Adrian Ionescu ETH • Kohei Itoh Keio U. • Seiichiro Kawamura Selete • Rick Kiehl U. Minn • Hiroshi Kotaki Sharp • Franz Kreupl Qimonda • Nety Krishna AMAT • Zoran Krivokapic AMD • Phil Kuekes HP • Lou Lome IDA • Hiroshi Mizuta U. Southampton • Murali Muraldihar Freescale • Fumiyuki Nihei NEC • Dmitri Nikonov Intel • Wei-Xin Ni NDL • Yaw Obeng NIST • Dave Roberts Air Products • Kaushal Singh AMAT • Kentaro Shibahara Hiroshima U. • Sadas Shankar Intel • Thomas Skotnicki ST Me • Satoshi Sugahara Tokyo Tech • Shin-ichi Takagi U. Tokyo • Luan Tran Micron • Ken Uchida Toshiba • Yasuo Wada Waseda U. • Rainer Waser RWTH A • Franz Widdershoven NXP • Jeff Welser NRI/IBM • Philip Wong Stanford U. • Kojiro Yagami Sony • David Yeh SRC/TI • In-Seok Yeo Samsung • Makoto Yoshimi SOITEC • In-K Yoo SAIT • Peter Zeitzoff Freescale • Yuegang Zhang Intel • Victor Zhirnov SRC

  6. Emerging Research Memory Technology Discussion Recommend Technology Entries Transfer/Add/Drop from Section (Spin Torque transfer MRAM – ERD or PIDS?) Memory Application Categories ERD/ERM Remaining Workshops Purpose, Topics and Funding When and Where Format and Length – Integration with ERD FxF Business Mtgs Review December Kamakura/Washington ERD Meetings Decisions Action Items Remaining Issues Discuss ERM/ERD Collaboration & Issues ERD Working GroupObjectives (1/2)

  7. Identify & Discuss other cross ITWG Issues Design & Systems Drivers PIDS FEP Modeling & Simulation Metrology More than Moore Discuss other key issues: How to expand scope to include MtM? Should we continue to include “failing” technologies in Logic? How to include “Best Demonstrated Parameters” for TE’s? (same or different devices?) Critical Review: Change message to more positive guide to the research addressing what may be fundamentally limited TE’s or continue our fundamental critiques? Discuss Japan’s ERD WG inputs on Guiding Principles ERD Working GroupObjectives (2/2)

  8. 14:00 Review meeting objectives and agenda Hutchby 14:10 Emerging Research Memory Tech Discussion Zhirnov Recommend Tech Entries Transfer/Add/Drop Memory Application Categories 14:30 Remaining ERD/ERM Workshops Hutchby, Garner Purpose, Topics and Funding When and Where Format & Length – Integration with Bus. Mtgs 15:15 Review Kamakura/Washington ERD Meetings Hutchby Decisions Action Items Remaining Issues 15:45 Discuss ERM/ERD Collaboration & Issues Garner, Hutchby 16:15 Discuss other Cross-ITWG Issues ERD X-TWG Leaders 17:00 Discuss Japan ERD’s input on Guide Principles Uchida 17:30 Discuss other Key Issues Hutchby et al 18:00 Adjourn ERD ITWG Working GroupAgenda

  9. ERD Subcommittees Leader(s) Chapter Chair Hutchby Memory Zhirnov Logic Bourianoff Architecture Cavin Editors Hutchby, Bourianoff, Cavin and Zhirnov ITRS Liaisons PIDSNg, Hutchby FEP Herr Modeling & Simulation Shankar Materials Shankar Metrology Herr Design Yeh/Bourianoff More than Moore Brillouet 2008 ERD Working Group Organization

  10. April 2 – Memory Workshop April 2 – ERD Business Meeting April 3 – 4 – ITRS Meetings (no public conference) June ? – ERD Presentation draft for July 16 Conference due to Linda Wilson July 10 – 11 Architecture Workshop & ERD Business Meeting July 12 – ERD Business Meeting July 14 – 15 – ITRS Meetings July 16 – ITRS Public Conference September 22nd – Logic Workshop September 23rd – ERD Business Meeting? August ? – ERD Chapter Update Material Due* September ? – 2008 ITRS Update Content Frozen* December 7 – 2009 ERD Chapter Kickoff Meeting in Seoul, Korea? December 7 – 9 ITRS Meeting in Seoul, Korea December 10 – ITRS Public Conference in Seoul, Korea December 14 – 2009 ERD Chapter Kickoff Meeting in San Francisco @IEDM * ERD typically uses the “update year” to prepare for the following “chapter re-write year (i.e. 2009” and does not provide an update. 2008 ERD Update Schedule

  11. 2008 ERD/ERM Workshops

  12. Action Items (1/2)

  13. Action Items (2/2)

  14. ERD/ERM Collaboration Discussion

  15. ETB Memory transition Alternate Channel Materials Floating Body Memory MRAM and NW PCRAM Cross ERD/PIDS Collaboration Discussion

  16. Alternate Channel Materials ETB Memories ERD/FEP Collaboration Discussion

  17. Transport in Alternative Channel Materials (e.g. strain effects in p-type III-V’s and Ge) Commercially available DFT Models with Excited States Transport in ultra-scaled devices – good model for scattering to ballistic transition needed. Need to simulate I-V curves for on-state and off-state memory devices listed in ERD. Device and process modeling for above bullets. ERD/Model & Simulation Discussion

  18. Boundary between analog and digital devices – where are the opportunities for analog devices in a power constrained environment? How would availability of 3-D transistors or 3-D functions change your lives? (Nano-wires oriented vertically). What design tool innovations are required to incorporate new devices. Newer current sensing with Ion/Ioff of 10 or less? ERD/Design Discussion

  19. We are recommending consideration of 8-12 bits precision analog for main stream info processing High precision A/D conversion (8-12 bits) Spin torque oscillators and/or RTD oscillators? Where’s the model for STO’s? Do you consider MEMS RF switches? ERD/RF & Analog MS Discussion

  20. Small geometrical metrologies, obtaining a reasonable signal/noise ratio – study, determine, and manage noise sources. Extract the signal from noise. Issue of contamination of nano-scaled devices Time resolved magnetic measurements. Ability to perform real time measurements, e.g. phase transitions. Wide band characterizations of rf devices – above 100 GHz. Questions from Metrology PCM – Near mfg? MRAM – Near mfg? – In production. Spin torque RAM Contamination - ERD/Metrology Collaboration Discussion

  21. Critical Review of 2007 ERD • Toshiro Hiramoto • University of Tokyo • Guiding Principles • Scope • Difficult Challenges • Taxonomy

  22. Guiding Principles: Beyond CMOS 1. Computational State Variable(s) other than Solely Electron Charge 2. Non-thermal Equilibrium Systems 3. Novel Energy Transfer Interactions 4. Nanoscale Thermal Management 5. Sub-lithographic Manufacturing Process 6. Emerging Architectures In this case, architecture is the functional arrangement of interconnected devices that includes embedded computational components. These architectures could utilize, for special purposes, novel devices other than CMOS to perform unique functions. Does this GP include both topics below or just the second topic? • New architectures with conventional MOSFET devices • New architectures with beyond CMOS devices onCMOS infrastructure.

  23. Guiding Principles – cont’d (a) First five principles - The same as the 2005 version - Well recognized as beyond CMOS guiding principles (b) The last principles - Divided into two principles or describe clearly that there are two approaches (?) (1) New architectures with conventional devices (2) New architectures with beyond CMOS devices on CMOS infrastructure.

  24. Research Needs (Beyond CMOS, US) • Information processing technologies using state variables other than charge? • Devices that operate out of equilibrium with the thermal bath? • Information transfer (i.e., interconnect) mechanisms that are not electromagnetic in nature? • Phonon engineering for advanced thermal management? • Directed self-assembly for information processing applications including size, shape and position control of complex nanostructures? • Devices that are amenable to non-Boolean logic? • Metrology and characterization for nanoscale information processing technologies? • Modeling and simulation for future information processing technologies? • Hybrid/heterogeneous information processing technologies including design methodologies? • Design and fabrication of very complex information processing technologies using defective/unreliable components? • Environmentally benign manufacturing materials and processes for nanoscale information processing technologies? • Fundamental limits dictated by physics for nanoscale information processing technologies? • Metrics to gauge the potential for success of nanoscale information processing technologies?

  25. New Research Needs (Japan) 14. More than Moore? 15. Memory 16. Functional CMOS design with beyond CMOS devices and new materials 17. Architecture with conventional devices - 3D- Memory/Logic - BDD 18. Self learning circuit network? - device - circuits - architecture

  26. Back up Slides

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