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ITRS Presentation PIDS ITWG Emerging Research Devices Hsin-Chu, Taiwan December 2, 2003

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ITRS Presentation PIDS ITWG Emerging Research Devices Hsin-Chu, Taiwan December 2, 2003

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  1. ITRS PresentationPIDS ITWGEmerging Research DevicesHsin-Chu, TaiwanDecember 2, 2003 Jim Hutchby - SRC

  2. PIDS Research Devices Working GroupParticipants • George Bourinaoff Intel/SRC • Joe Brewer U. Florida • Toshiro Hiramoto Tokyo U. • Jim Hutchby SRC • Mike Forshaw UC London • Tsu-Jae King UC Berkeley • Rainer Waser RWTH A • In Yoo Samsung • John Carruthers OGI • Joop Bruines Philips • Jim Chung Compaq • Peng Fang AMAT • Dae Gwan Kang Hynix • Makoto Yoshimi Toshiba • Kristin De Meyer IMEC • Tak Ning IBM • Philip Wong IBM • Luan Tran Micron • Victor Zhirnov SRC/NCSU • Ramon Compano Europe Com • Simon Deleonibus LETI • Thomas Skotnicki ST Me • Yuegang Zhang Intel • Kentaro Shibahara Hiroshima U. • Byong Gook Park Seoul N. U.

  3. Emerging Research DevicesIntroduction and Scope Cast a broad net to introduce readers to device and architecture concepts for information processing --- Concept --- not hardened solutions Identify --- not endorse --- and quantify (new) Include Stimulate --- and assess/critique (new)

  4. Emerging Research DevicesIntroduction and Scope Broadened Scope Compared to 2001 Chapter --- New quantitative performance metrics --- potential versus to-date performance Provide in-depth critical assessment --- key application driven questions/issues

  5. New Memory and Logic Technologies New Architecture Technologies Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS

  6. : Projected forward “Best Case” MIT Antoniadis Bulk-Si Performance Trends Maintaining historical CMOS performance trend requires new semiconductor materials and structures by 2008-2010... Earlier if current bulk-Si data do not improve significantly.

  7. Single Gate Non-classical CMOS

  8. Multiple Gate Non-classical CMOS

  9. Technology Enhancements for High Performance Calculations performed using MASTAR – ST Microelectronics – T. Skotnicki

  10. New Memory and Logic Technologies New Architecture Technologies Nanotubes Molecular devices Quantum cellular automata Emerging Information Processing Concepts Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS

  11. Emerging Research DevicesRequirements & Motivations for Beyond CMOS Fundamental Requirements • Energy restorative functional process (e.g. gain) • Compatible with CMOS • At or above room temperature operation Compelling Motivations • Functionally scaleable > 100x beyond CMOS limit • and High information processing rate and throughput • or Minimum energy per functional operation • or Minimum, scaleable cost per function

  12. Emerging Research Memory Devices

  13. Emerging Research Logic Devices

  14. Scaling Limit of Charge Based SwitchAn Example of Critical Assessment Observations • Transistor critical dimension limited to ~ 1 nm (In the 2003 ITRS physical gate length = 7 nm for 2018) • Power density, not critical dimension, limits gate density to ~ 1 x 109 gates/cm2 • For the ITRS density and switching time, CMOS is approaching the maximum power efficiency

  15. Technology Performance and Risk Evaluation Emerging Research Memory Devices

  16. Technology Performance and Risk Evaluation Emerging Research Logic Devices

  17. Emerging Research DevicesSummary • Potential solutions for device structures necessary to achieve the advanced nodes (< 45-nm) identified • For the ITRS gate density and switching time - • Power density (not switch size) limits charge based logic density and performance • CMOS is approaching the maximum power efficiency • Emerging Research Device Technologies will extend CMOS into new application domains