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Digital System Design by Verilog

Digital System Design by Verilog. University of Maryland ENEE408C. HDL Compiler Unsupport (Do NOT use in your verilog code). delay (# will ignore) initial ( add a reset signal ) repeat wait fork event deassign force release. Basic Rules in Synthesis. Synthesizable HDL coding.

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Digital System Design by Verilog

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  1. Digital System Design by Verilog University of Maryland ENEE408C

  2. HDL Compiler Unsupport (Do NOT use in your verilog code) • delay (# will ignore) • initial ( add a reset signal ) • repeat • wait • fork • event • deassign • force • release

  3. Basic Rules in Synthesis

  4. Synthesizable HDL coding always @(posedge a) out = in1; always @(posedge b) out = in2; Warning! Synthesized function will go wrong *Can not assign identical reg in more than one blocks

  5. Combinational Logic always @(sel) if (sel==1) out = in1; else out = in2; *Warning !! in1 out in2 always @(sel or in1 or in2) if (sel==1) out = in1; else out = in2; sel Multiplexer

  6. Register always @(posedge clk or posedge reset) if ( reset ) out <=0; else out <= a & b; Register with asynchronous reset always @(posedge clk) if ( reset ) out <=0; else out <= a & b; Register with Synchronous reset

  7. Inferred Latch always @(sel or in) if (sel==1) out = in; Incomplete if statement always @(sel or in) case ( sel ) 2’b00: out=in1; 2’b01: out=in2; 2’b10: out=in3; endcase Not a full case

  8. Finite State Machine always @(current_state or data1 or data2) case ( current_state ) S0: begin result=data1; next_state=S1; end S1: ....... endcase Combinational logic next_state generator always @(posedge clk) if ( reset ) current_state=S0; else current_state=next_state; Sequential logic state transition

  9. Few more rulesVerilog Restrictions for Synthesis • Simulatable designs are not necessarily synthesizable. • Synthesizable constructs are tool dependent • Use only few HDL commands. • case if else concurrent and sequential statements • Continuous assignment is synthesizable • An unknown(x) is not synthesizable when is used in comparison. • assign y=(a===1’bx)?c:1; (No) • assign y=(a==b)?1’bx:c; (Yes)

  10. Use non-blocking assignment for edge-sensitive behavior • Keep the intended circuit architecture in mind during design description. • Using C-like programming style increases the silicon area dramatically. • Type conversions and test stimuli definitions cannot be synthesized. • Smallest HDL code does not imply smallest silicon. • Describe the architecture clearly. • Cover all possible states within a if-else or case statement. • Loops with • Do not use nested loops for circuit description

  11. Do not define functions when instantiating parts within one entity. • Make extensive use of comments. • Use headers for all modules, functions • Explain the operating modes of the modules • Explain all input and output signals • Compiler directives reside within comments

  12. Useful Links • http://www-cad.eecs.berkeley.edu/~chinnery/synthesizableVerilog.html • http://home.europa.com/~celiac/samples.html

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