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The Future in 8-Bit Microcontrollers

The Future in 8-Bit Microcontrollers. The AVR is. … the first new 8-bit MCU architecture to be launched in the last 12 years … a new design, not based on an architecture from the 70’s … designed to be fast and code efficient instead of backwards compatible

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The Future in 8-Bit Microcontrollers

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  1. The Future in 8-Bit Microcontrollers

  2. The AVR is... • … the first new 8-bit MCU architecture to be launched in the last 12 years • … a new design, not based on an architecture from the 70’s • … designed to be fast and code efficient instead of backwards compatible • … designed to meet today’s and the future’s demand for processing power and memory size • … taking advantage of today’s semiconductor technology • … designed in co-operation with C compiler experts to be C code efficient

  3. The AVR Offers... • … Industry’s Highest 8-bit Performance • … a Real 8-Bit RISC Architecture • … Low Power • … a broad Family of MCUs • … a Variety of Peripherals • … excellent C Language Code Density • … in-System Programmable Flash and EEPROM

  4. This is how it’s done • Four Memory Pointers • Linear (Non Paged) Memories • 32 General Purpose Registers • Harvard Architecture • True single external clock cycle execution • A very rich and powerful instruction set • Powerful data addressing modes optimized for the C language • Utilization of Atmel’s 14 years of experience in Non-Volatile Memories

  5. Traditional RISC Traditional Line of Compromise Traditional CISC AVR Breaking Traditions Code Size Speed

  6. AVR Block Diagram

  7. AVR Register File R0 R1 R2 R3 R26 XL X Pointer R27 XH R28 YL Y Pointer R29 YH R30 ZL Z Pointer R31 ZH Register File

  8. Direct Register - ALU Connection Register File Register operations take ONE clock pulse on the EXTERNAL clock input ALU

  9. 1 2 1 2 1 2 1 2 Execute 2 Instructions Done! PIC Done! HC05 Done! ‘C51 Done!

  10. The Three AVR Families • MEGA AVR ATmegaxxx ( 16KB - 128KB) • Targets complex applications with requirements for large program memories • Classic AVR AT90Sxxxx ( 1KB- 8KB ) • Targets medium-range applications where high throughput and low power are important • Tiny AVR ATtinyxx ( 1KB - 2KB ) • Targets cost-sensitive applications in the very low end of the 8-bit MCU market

  11. Available AVR Products ‘S1200 ‘S2323 ‘S2343 ‘S2313 ‘S4414 ‘S4434 PINS 20 8 8 20 40/44 40/44 FLASH 1KB 2KB 2KB 2KB 4KB 4KB SRAM 0 128B 128B 128B 256B 256B EEPROM 64B 128B 128B 128B 256B 256B UART - - - YES YES YES PWMs 0 0 0 1 2 3 A/D Converter - - - - - 8@10-bit YES RTC - - - - - SAMPLES NOW NOW NOW NOW NOW NOW PRODUCTION NOW NOW NOW NOW NOW NOW

  12. Available AVR Products ‘S8515 ‘VC8534 ‘S8535 PINS 40/44 48 40/44 FLASH 8KB 8KB 8KB 512B 256B 512B SRAM EEPROM 512B 512B 512B UART YES NO YES PWMs 2 3 - A/D Converter - 6@10-bit 8@10-bit - RTC - YES SAMPLES NOW NOW NOW NOW NOW NOW PRODUCTION

  13. Available megaAVR Products mega603 mega103 mega163 mega161 Mega 83 40/44 PINS 40/44 40/44 64 64 16KB 16KB 16KB FLASH 128KB 64KB SRAM 1KB 1KB 4KB 4KB 512B 1KB 512B 4KB 2KB 512B EEPROM 2 2 2 UART YES YES 4 4 4 PWM 4 4 8@10-bit 8@10-bit 8@10-bit 8@10-bit A/D Converter YES YES YES YES RTC YES SAMPLES NOW NOW NOW 2Q00 2Q00 3Q00 3Q00 3Q00 NOW PRODUCTION NOW

  14. AVRMCU’s Available cont. 90S2333 90S4433 PINS 28/32 28/32 2KB FLASH 4KB 128B 128B SRAM EEPROM 128B 256B UART YES YES PWM 1 1 6@10-bit 6@10-bit A/D Converter YES YES ISP SAMPLES NOW NOW PRODUCTION NOW NOW

  15. tinyAVR Roadmap tiny19 tiny15L tiny11 tiny28 tiny12 tiny22 tiny10 8 PINS 8 8 8 28 8 28 FLASH 1KB 1KB 1KB 1KB 2KB 2KB 1KB* 0B 0B 0B 0B 0B 128B 0B SRAM - - - - 128B EEPROM 64B 64B ISP NO NO YES YES NO YES NO I/O’s 6 6 6 6 20 20 5 4@10-bit A/D Converter - - - - - 2, 1 PWM 1 1 1 1 1 1 T/C SAMPLES 1Q00 NOW 1Q00 NOW 2Q00 NOW NOW 3Q00 PRODUCTION 2Q00 NOW 2Q00 2Q00 3Q00 NOW *QuickFlash Version of tiny11

  16. AVR Direction • 16KB MEGA AVR • Application Specific Standard Products (ASSPs) • Battery Charger • USB Device • Remote Control Device • The first TINY devices • Pin Counts: 8 - 28 • Program Memories: 0.5 - 2K

  17. A C-Code Example The following example illustrates the AVR benefits in terms of: Code Size Throughput Power Consumption

  18. A Small C Function /* Return the maximum value of a table of 16 integers */ int max(int *array) { char a; int maximum=-32768; for (a=0;a<16;a++) if (array[a]>maximum) maximum=array[a]; return (maximum); }

  19. AVR Assembly output ; 7. for (a=0;a<16;a++) LDI R18,LOW(0) LDI R19,128 CLR R22 ?0001: CPI R22,LOW(16) BRCC ?0000 ; 8. { ; 9. if (array[a]>maximum) MOV R30,R22 CLR R31 LSL R30 ROL R31 ADD R30,R16 ADC R31,R17 LDD R20,Z+0 LDD R21,Z+1 CP R18,R20 CPC R19,R21 BRGE ?0005 ; 10. maximum=array[a]; MOV R18,R20 MOV R19,R21 ?0005: INC R22 RJMP ?0001 ?0000: ; 11. } ; 12. return (maximum); MOV R16,R18 MOV R17,R19 ; 13. } RET Code Size: 46 Bytes, Execution time: 335 cycles

  20. C51 Assembly Output ; FUNCTION _max (BEGIN) ;---- Variable 'array' assigned to Register 'R1/R2/R3' ---- ; SOURCE LINE # 4 ; SOURCE LINE # 5 ; SOURCE LINE # 7 MOV maximum,#080H MOV maximum+01H,#00H ; SOURCE LINE # 9 ;---- Variable 'a' assigned to Register 'R5' ---- CLR A MOV R5,A ?C0001: ; SOURCE LINE # 10 ; SOURCE LINE # 11 MOV A,R5 MOV R7,A RLC A SUBB A,ACC MOV R6,A MOV A,R7 ADD A,ACC MOV R7,A MOV A,R6 RLC A MOV DPL,R7 MOV DPH,A LCALL ?C?ILDOPTR MOV R7,A MOV R6,B SETB C SUBB A,maximum+01H MOV A,maximum XRL A,#080H MOV R0,A MOV A,R6 XRL A,#080H SUBB A,R0 JC ?C0003 ; SOURCE LINE # 12 MOV maximum,R6 MOV maximum+01H,R7 ; SOURCE LINE # 13 ?C0003: INC R5 CJNE R5,#010H,?C0001 ?C0002: ; SOURCE LINE # 14 MOV R6,maximum MOV R7,maximum+01H ; SOURCE LINE # 15 ?C0005: RET ; FUNCTION _max (END) ?C?ILDOPTR: CJNE R3,#0x01,0x195 MOV A,0x82 ADD A,R1 MOV 0x82,A MOV A,0x83 ADDC A,R2 MOV 0x83,A MOVX A,@DPTR MOV OxF0,A INC DPTR MOVX A,@DPTR RET JNC 0x1A0 MOV A,R1 ADD A,0x82 MOV R0,A MOV 0xF0,@R0 INC R0 MOV A,@R0 RET CJNE R3,#0xFE,0xAD MOV A,R1 ADD A,0X82 MOV R0,A MOV A,@R0 MOV 0xF0,A INC R0 RET MOV A,0X83 ADD A,R2 MOV 0X83,A MOV A,R1 MOVC A,@A+DPTR RET Code Size: 112 Bytes, Execution time: 9384 cycles

  21. HC11 Assembly output ; 7. for (a=0;a<16;a++) TSX LDD #-32768 STD 1,X CLR 0,X ?0001: LDAA 0,X CMPA #16 BHS ?0000 ; 8. { ; 9. if (array[a]>maximum) PSHY TAB CLRA LSLD TSX ADDD 0,X XGDX LDD 0,X TSX STD 5,X INS INS CPD 3,X BLE ?0005 ; 10. maximum=array[a]; STD 3,X ?0005: TSX INC 0,X BRA ?0001 ?0000: ; 11. } ; 12. return (maximum); LDD 1,X ; 13. } PULX PULX INS PULY RTS Code Size: 57 Bytes, Execution time: 5244 cycles

  22. PIC16C74 Assembly output bcf 3,5 movwf ?a_maxnum& (0+127) ;MAX_MAIN.C: 4: char a; ;MAX_MAIN.C: 5: int maximum=-32768; clrf (?a_maxnum+2)& (0+127) movlw 128 movwf (?a_maxnum+3)& (0+127) ;MAX_MAIN.C: 7: for (a=0;a<16;a++) clrf (?a_maxnum+1)& (0+127) l2 ;MAX_MAIN.C: 8: { ;MAX_MAIN.C: 9: if (array[a]>maximum) bcf 3,5 movf (?a_maxnum+1)& (0+127),w addwf (?a_maxnum+1)& (0+127),w addwf ?a_maxnum& (0+127),w movwf 4 movf 0,w movwf btemp incf 4 movf 0,w movwf btemp+1 movf (?a_maxnum+3)& (0+127),w xorlw 128 movwf btemp+2 movf btemp+1,w xorlw 128 subwf btemp+2,w btfss 3,2 goto u15 movf btemp,w subwf (?a_maxnum+2)& (0+127),w u15 btfsc 3,0 goto l5 ;MAX_MAIN.C: 10: maximum=array[a]; bcf 3,5 movf (?a_maxnum+1)& (0+127),w addwf (?a_maxnum+1)& (0+127),w addwf ?a_maxnum& (0+127),w movwf 4 movf 0,w movwf (?a_maxnum+2)& (0+127) incf 4 movf 0,w movwf (?a_maxnum+3)& (0+127) l5 ;MAX_MAIN.C: 11: } bcf 3,5 incf (?a_maxnum+1)& (0+127) movlw 16 subwf (?a_maxnum+1)& (0+127),w btfss 3,0 goto l2 ;MAX_MAIN.C: 12: return (maximum); bcf 3,5 movf (?a_maxnum+3)& (0+127),w movwf btemp+1 movf (?a_maxnum+2)& (0+127),w movwf btemp return Code Size: 87 Bytes, Execution time: 2492 cycles

  23. Performance Comparison: • AT90S8515 @ 8 MHz • 80C51 @ 24 MHz • 68HC11A8 @ 12 MHz • PIC16C74 @ 20 MHz Normalized figures given in parentheses

  24. Some Conclusions on THIS Case • The C51 would have to run at 224 MHz to match the 8 MHz AVR. • The HC11 is quite code efficient, but delivers only one 10th of the processing power at 2.5 times the current consumption • The PIC is a fast microcontroller, but the AVR delivers more than 3.5 times higher throughput per mW.

  25. What made the AVR do better? • Excellent support for 16-bit arithmetics. (Zero-Flag Propagation on Compare) • A lot of registers which eliminate move to and from SRAM • Single Cycle execution

  26. An Architecture Optimized for High Level Language

  27. High Level Languages • Increased importance for Microcontrollers • Time to market • Simplified maintenance • Portability • Learning time • Reusability • Libraries • Potential drawbacks • Increased code size • Decreased speed

  28. AVR Architecture and Instruction Set Influenced by IAR • Architecture co-designed with IAR systems through several iterations: • Compiler development project initiated before architecture and instruction set frozen • Compiler expert’s advice implemented in hardware • Potential HLL bottlenecks identified and removed

  29. C-like Addressing Modes (1) Auto Increment/Decrement: C Source: unsigned char *var1, *var2; *var1++ = *--var2; Generated code: LD R16,-X ST Z+,R16

  30. C-Like Addressing Modes (2) Indirect with Displacement: • Efficient for accessing arrays and structs • Autos placed on Software Stack

  31. Four Memory Pointers SRAM • Code efficient memory to memory copy • Pointer reloading is minimized • Separate stacks for return addresses and local variables X Y Z SP

  32. 16 and 32-Bit Support • Carry instructions • Addition and Subtraction • Register/register • Register/immediate • Zero flag propagation Enables fast and code efficient operations on 16 and 32-bit data types

  33. E1 sub r0,r2 03 sbc r1,r3 Subtract Two 16-Bit Values Without Zero Flag Propagation R1:R0 - R3:R2 ($E104 - $E101) R1 R0 Z E1 04 X 03 0 00 1 Wrong!

  34. E1 sub r0,r2 03 sbc r1,r3 Subtract Two 16-Bit Values With Zero Flag Propagation R1:R0 - R3:R2 ($E104 - $E101) R1 R0 Z E1 04 X 03 0 00 0 Correct!

  35. Multi-Byte Compare • Compare with carry instruction • Zero-flag propagation • No restoring necessary • All conditional branches available after compare Example: 32-bit compare CP R16,R24 CPC R17,R25 CPC R18,R26 CPC R19,R27

  36. Switch Support • Switches are very frequently generated by CASE tools • Conventional straight-forward approaches are generally inefficient • Compact switch constructions take advantage of the AVR’s indirect jumps • General library routines in the compiler manages switches efficiently

  37. Compiler Features • Fully compatible with the ANSI standard • All required data types supported • Fully re-entrant code • General optimizations • AVR specific optimizations • AVR specific extensions

  38. Optimization • Code and Speed optimization • C and Assembly level optimizations • Algebraic identities • Common subexpression elimination • Removal of branch chains • Condition reversal • Constant folding • Register allocation • Bit operations • Peephole optimizations • Cross jumping and hoisting • Removal of unreachable code • Redundant assignment removal

  39. Summary • AVR Architecture originally designed with High Level Languages in mind • Architecture tuned for C in co-operation with C-compiler experts • Resulting compiler generates highly efficient code

  40. AVR Peripherals A closer look at some of the on-chip modules

  41. I/O Ports General Features • Push-Pull Drivers • High Current Drive (sinks up to 20 mA) • Pinwise Controlled Pull-Up Resistors • Pinwise Controlled Data Direction • Fully Synchronized Inputs • Three Control/Status Bits per Bit/Pin • Real Read-Modify-Write

  42. 3 Control/Status Bits per Pin • DDRx Data Direction Control Bit • PORTx Output Data or Pull-Up Control Bit • PINx Pin Level Bit X = A, B, C, ...

  43. I/O Pin Block Diagram DDRx 0 Pull-Up PORTx 0 PINx Physical Pin X X Direction: INPUT Pull-Up: OFF (Tri-State)

  44. Why Three Addresses? Why not let WRITE PORTx write the LATCH and READ PORTx read the PINS? (just like Microchip, Hitachi, Motorola...) A Two-Address Port Will Give You Trouble with Read-Modify-Write

  45. The problem with Two-Addresses • Read-Modify-Write writes an unknown value to the bits that are inputs. • If two successive Read-Modify-Writes are performed, the results from the first one might get corrupted. • When the latch controls the pull-up for input lines, a read-Modify-Write will TURN OFF the pull-ups for input lines that are low.

  46. From the PIC16C64 Datasheet: “Reading the PORT register, reads the values of the PORT pins. Writing to the PORT register writes the value to the PORTB latch. When using read modify write instructions (ex. BCF, BSF, etc.) on a PORT, the value of the PORT pins is read, the desired operation is done to this value, and the value is then written to the PORT latch” .” … “…care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction … otherwise, the previous state of that pin may be read into the CPU rather than the new state … it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.”

  47. From HITACHI’s H8/300 Programming Manual: “BSET, BCLR, … are read-modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are appliedto registers with write-only bits and to the I/O port registers.” … “Programming Solution: The switching of the pull-ups can be avoided by storing the same data both in the port data register and in a work area in RAM”

  48. UART Features • Full Duplex • 8 or 9 Data Bits • Framing Error Detection • False Start Bit Detection • Noise Canceling • High BAUD Rates at low XTAL FrequenciesE.g. 115,200 BAUD at 1.8432 MHz • Generates the BAUD rate you need • Separate BAUD rate timer • Three Interrupts with Separate Vectors

  49. ADC Features • Successive approximation w/ sample & hold • Up to 8 single ended channels and up to 7 differential channels • 10-Bit resolution • Configurable conversion time • Accuracy: • down to 65 ms conversion time: 10 bits ± 0.5 LSB • down to 12 msconversion time: 8 bits ± 0.5 LSB • Free-run and single conversion modes • Interrupt on conversion complete • CPU Turn-Off Noise Reduction

  50. Sleep Modes • Idle Mode • Power Down Mode • Power Save Mode (Parts with RTC) Feb 98

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