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Design and Simulation of an 8-Bit ALU Utilizing Han-Carlson Carry Network

This project details the design and simulation of an 8-bit Arithmetic Logic Unit (ALU) using a Han-Carlson carry network, achieving a clock frequency of 200 MHz with a power consumption of 25.28 mW. The ALU is capable of performing multiple operations, including addition, subtraction, and logical operations on two 8-bit numbers. The project includes an analysis of gate widths, timing verification, and layout extraction, revealing key insights and lessons learned during the design process while meeting all specifications.

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Design and Simulation of an 8-Bit ALU Utilizing Han-Carlson Carry Network

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  1. 8-Bit ALU Kin Fu Tang Robert Last Joseph Roosma Adnan Alam Advisor: David W. Parent May 8, 2006

  2. Agenda • Abstract • Introduction • Purpose • Simple Theory • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • An 8-bit ALU using a Han-Carlson carry network was designed. It was shown through simulations to operate at a clock frequency of 200MHz, using 25.28mW of Power and requiring an area of XxX mm2

  4. Introduction • An ALU is an important building block in digital systems which carries out the basic arithmetic and logic. • Depending on the supplied control signals, the ALU is designed to carry out the following operations on two 8-bit numbers: ADD, SUB, AND, OR, XOR, NAND, NOR, and many others.

  5. Block Diagram 8-bit Input DFF AOI3333 (G, HS) Control Signals (ADD, OR, etc.) Han-Carlson Carry Network XOR DFF 8-bit Output

  6. Function Table

  7. Summary of Results • Determination of Gate Widths • Final schematic, and • Simulations: NC Verilog and SPICE • Final layout • Verification of layout and extraction.

  8. Longest Path Calculations

  9. Schematic - Overall LONGEST PATH DFF INVERTER P G AOI3333 HAN-CARLSON NETWORK XOR BLACK CELL DFF

  10. Schematic & Layout – AOI3333

  11. Schematic & Layout – Black Cell

  12. Simulation – NC Verilog - ADD

  13. Simulation – NC Verilog - SUB

  14. Simulation – NC Verilog - OR

  15. Simulation – SPICE – Worst Case (Schematic) τPLH3.76ns

  16. Simulation – SPICE – 2-bit Addition(Schematic) Output Input

  17. Simulation – SPICE – Power Usage(Schematic) P = 25.28mW

  18. Layout - Overall DFF AOI3333 HAN-CARLSON NETWORK XOR DFF

  19. Verification – LVS Report

  20. Cost Analysis • Estimated time spent on each phase of the project: • Verifying logic: 8 hours • Verifying timing: 10 hours • Layout: 45 hours • Post extracted timing: 8 hours ___________TOTAL: 71 hours

  21. Lessons Learned • Start early. • Make sure that the overall logic works first (with actual transistors). • Once the overall timing is agreed upon, it’s hard to go back and make changes. • Use cell based design, it’s less confusing. • Save time for troubleshooting.

  22. Summary • An 8-bit ALU which operates at a clock frequency of 200MHz was designed and simulated. • All specifications (clock and power) were met.

  23. Acknowledgements • Dr. David Parent • Cadence Design Systems • Irma Alarcon (Lab Technician)

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