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RTL Processor Synthesis for Architecture Exploration and Implementation

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17 diapositives · 351 Views · Sep 25, 2014

This paper introduces a synthesis tool that utilizes the Language for Instruction-Set Architectures (LISA) to generate complete register-transfer level (RTL) architecture from high-level specifications. Traditional architecture description languages often overlook critical design parameters, leading to suboptimal solutions. Our approach maintains the flexibility of LISA while integrating SystemC for accurate hardware representation. We present two real-world case studies demonstrating the feasibility and efficiency of our method, highlighting its potential to address design space exploration challenges in application-driven designs.

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RTL Processor Synthesis for Architecture Exploration and Implementation
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  1. RTL Processor Synthesis for Architecture Exploration and Implementation Schliebusch, O. Chattopadhyay, A. Leupers, R. Ascheid, G. Meyr, H. Steinert, M. Braun, G. Nohl, A. Integrated Signal Process. Syst., Aachen Univ. of Technol., Germany Design, Automation and Test in Europe Conference and Exhibition 2004, pp. 156 - 160

  2. Abstract • Architecture description languages are widely used to perform architecture exploration for application-driven designs, whereas the RT-level is the commonly accepted level for hardware implementation. For this reason, design parameters such as timing, area or power consumption cannot be taken into consideration accurately during design space exploration. Design automation tools currently used to bridge this gap are either limited in the flexibility provided or only generate fragments of the architecture.

  3. Abstract (cont.) • This paper presents a synthesis tool which preserves the full flexibility of the architecture description language LISA, while being able to generate the complete architecture on RT-level using systemC. This paper also presents two real world architecture case studies to prove the feasibility of our approach.

  4. What’s the problem? • Architecture Description Languages (ADLs) often ignoring physical parameters in the design leads to suboptimal solutions or long redesign cycles • high level abstraction and physical parameter evaluation are both necessary

  5. Related Work • MIMOLA ,FlexWare • too close to the RTL • ISDL ,nML • each function unit one type exactly • PEAS-III ,ASIP-Meister ,Xtensa ,PICO • Predefined elements or architectures

  6. LISA module • Exploration and implementation based on LISA (Language for Instruction-Set Architectures)

  7. LISA module (cont.) • LISA module and correspondent HDL model component

  8. The HDL Synthesis Framework • Explicit Hardware Description • Implicit Hardware Description • Non-formalized Hardware Description

  9. Explicit Hardware Description • Explicit type of hardware description results from language elements • with a well defined semantics • define the underlying hardware • without ambiguity • RTL can be generated directly

  10. Explicit Hardware Description (cont.) • Example of Explicit Hardware Description

  11. Implicit Hardware Description • Implicit type of hardware description results from language elements • not self-explanatory • semantics is more general • deeper analysis of the complete is needed • additional info needs to be taken into account • Info may be from simulation scheduler

  12. Implicit Hardware Description (cont.) • Example of Implicit Hardware Description

  13. Non-formalized Hardware Description • The BEHAVIOR section can be considered as non-formalize description, enrich by LISA language elements • contain mainly plain ANSI-C code • the SystemC is used to generate RTL representation of the architecture

  14. Non-formalized Hardware Description (cont.) • Transformation of resources

  15. Experiments and Results • The LEON Architecture • the integer pipeline and memory configuration of the LEON were modelled in LISA • The automatically generated SystemC model and the reference model are synthesized with the Synopsys design compiler • The LISA model as well as the generated SystemC model have been verified with the microSparc Validation suite

  16. Experiments and Results (cont.) • The Infineon Technologies ASMD • Application-Specific Multi-rate DSP

  17. Conclusion • presented a methodology to fully generate a synthesizable RT-level hardware description from LISA • the gap can be bridged using the SystemC • the complete architecture can be generated from a single specification, without losing the flexibility • add an analysis and optimization step in the future work