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IO Connection Assignment and RDL Routing for Flip-Chip Designs

IO Connection Assignment and RDL Routing for Flip-Chip Designs. Jin-Tai Yan, Zhi -Wei Chen. ASPDAC.2009. Outline. Introduction Problem Formulation IO Connection Assignment for Flip-Chip Designs RDL Routing for Flip-Chip Designs Experimental Results Conclusions. Introduction.

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IO Connection Assignment and RDL Routing for Flip-Chip Designs

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  1. IO Connection Assignment and RDL Routing for Flip-Chip Designs Jin-Tai Yan, Zhi-Wei Chen ASPDAC.2009.

  2. Outline • Introduction • Problem Formulation • IO Connection Assignment for Flip-Chip Designs • RDL Routing for Flip-Chip Designs • Experimental Results • Conclusions

  3. Introduction • As the circuit complexity increases and the feature size decreases, flip-chip (FC) package is introduced to meet the higher integration density and the larger I/O counts of modern VLSI circuits. • However, the placement of the I/O pads in IC designs is not well mapped onto the bump balls in flip-chip designs.

  4. Introduction • Hence, an extra metal layer, Re-Distribution Layer (RDL), is used to redistribute the IO pads to the bump balls without changing the placement of the IO pads.

  5. Problem Formulation • In general, RDL routing in flip-chip designs is only allowed to route all the connections in a single layer. • Two-pin net or multiple-pin net. • The capacity constraints between any pair of adjacent bump balls. • Minimize the total wirelength. Wire Crossing

  6. IO Connection Assignment for Flip-Chip Designs • capacity constraint : 2

  7. Algorithm Preview • Two-phase routing approach

  8. IO Connection Assignment for Flip-Chip Designs • Find the Delaunay triangulation for IO buffers

  9. IO Connection Assignment for Flip-Chip Designs • Find the Voronoi diagram for IO buffers

  10. IO Connection Assignment for Flip-Chip Designs • The IO buffer in any Voronoi polygon containing at least one IO ball can be assigned onto the closer IO ball inside the Voronoi polygon.

  11. IO Connection Assignment for Flip-Chip Designs • Delete the connected IO buffer and balls and constructed a new Voronoi diagram using the remaining IO buffers. And assign IO buffer to IO ball again.

  12. IO Connection Assignment for Flip-Chip Designs

  13. Algorithm • Two-phase routing approach

  14. IO Connection Assignment for Flip-Chip Designs • For increasing the routability, exchanged a pair of IO connections by using the pair-exchange operation. • For routability • For wirelength

  15. IO Connection Assignment for Flip-Chip Designs

  16. Algorithm • Two-phase routing approach

  17. IO Connection Assignment for Flip-Chip Designs • The IO ball which is the closest to the geometrical center of all the IO buffers is selected as the common IO ball of the set of IO buffers with the same number.

  18. Algorithm • Two-phase routing approach

  19. RDL Routing for Flip-Chip Designs • In the global wire assignment, the routing regions of all the IO connections in a routing plane can be easily constructed.

  20. RDL Routing for Flip-Chip Designs • Global wire assignment • The global wire of the IO connection will be assigned as a global feasible path through the covered edges inside its routing region under the capacity constraint by the probabilistic congestion control[7].

  21. RDL Routing for Flip-Chip Designs • Steiner-point assignment • The two global wires located in the same quadrants or adjacent quadrant may assign a Steiner point to reduce the total wirelength.

  22. RDL Routing for Flip-Chip Designs

  23. Algorithm • Two-phase routing approach

  24. RDL Routing for Flip-Chip Designs • Crossing-point assignment • If the capacity constraint inside a passing edge is satisfied, the crossing point of any global wire inside a passing edge must be further assigned.

  25. RDL Routing for Flip-Chip Designs • River routing for physical path assignment • According to the result of the crossing-point assignment, the physical paths of the two-terminal connections can be routed by using a river routing algorithm

  26. RDL Routing for Flip-Chip Designs • Maze routing • The physical paths of the unassigned IO connections can be further obtained by running a maze-routing algorithm

  27. AlgorithmReview

  28. Experimental Results • Six tested circuits with random locations of IO buffers are generated. • For thecomparison of the routing result: • a greedy IO connection assignment approach • a single-layer BGA global router[8]

  29. Conclusions • This paper propose an O(n2) IO assignment and RDL routing algorithm and guarantee 100% routability if the capacity constraint is permitted. • The experimental results show that our RDL routing algorithm is very effective for flip-chip designs.

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