Chapter 5: Operation Modes and Memory Expansion

1. Chapter 5: Operation Modes and Memory Expansion The 68HC11 Microcontroller Han-Way Huang Minnesota State University, Mankato

2. The 68HC11 Operation Modes - Single chip mode: a mode in which the 68HC11 functions without external address and data buses. The 68HC11 has 5 I/O ports (A, B, C, D, and E) to use in this mode. - Expanded mode: a mode in which the 68HC11 has the capability to access a 64KB address space. In this mode, port B is used as the upper address signals (A15-A8) and port C is used as time-multiplexed address/data bus (A7/D7-A0/D0). Only three I/O ports are available for direct use. - Special test mode: mainly used by Motorola in fabrication testing. - Special Bootstrap mode: a mode in which a bootstrap ROM is enabled. The bootstrap ROM contains a loader program that will be executed after the RESET signal is going high and this program will load in a 256-byte program from the SCI subsystem to the on-chip SRAM and then transfer the CPU control to that loaded program. Establishment of the operation mode On the rising edge of the RESET, the voltage levels on pins MODA and MODB are latched into the HPRIO register, which determines the operation mode of the 68HC11.

3. Memory Technologies and Terminology 1. Nonvolatile and volatile memories: differentiated by whether a memory component will lose its contents when the power is removed. 2. ROMs and RAMs: differentiated by whether a a memory component can be read/write from/into for roughly the same amount of time. 3. Dynamic and Static RAMs: differentiated by whether a RAM requires periodic refresh operation in order to maintain its stored information. 4. Memory capacity: the total number of bits that a memory chip contains. 5. Memory organization: describes the number of bits that can be accessed from a memory chip in one operation. The organization is specified as m  n, where m is the total number of locations and n is the number of bits in each location.

4. Example 5.1 Using the following memory chips, how many SRAM chips will be needed to build a 512KB, 16-bit memory system for a 16-bit microprocessor? a. 256K × 1 SRAM b. 256K × 4 SRAM c. 256K × 8 SRAM d. 64K × 8 SRAM Solution: a. Sixteen SRAM chips with × 1 organization are needed to construct a 16-bit memory system. 16 256K × 1 chips are required to build a 512KB 16-bit memory system. b. Four SRAM chips with × 4 organization are needed to construct a 16-bit memory system. Four 256K × 4 SRAM chips are needed to construct a 512 KB 16-bit memory system. c. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory system. Two 256K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system. d. Two SRAM chips with × 8 organization are needed to construct a 16-bit memory system. Eight 64K × 8 SRAM chips are needed to construct a 512 KB 16-bit memory system.

5. Reposition 68HC11 on-chip SRAM and I/O registers - The upper four bits of the INIT register reposition the on-chip SRAM to the beginning of any 4KB page - The lower four bits of the INIT register reposition the I/O registers to the beginning of any 4KB page. - The repositioning of SRAM and I/O registers can only be done within 64 E clock cycles after reset. Example 5.2 Reposition the 68HC11 on-chip SRAM to $2000-$20FF and remap I/O registers to $3000-$303F. Solution: Set the upper four bits and lower four bits of the INIT register to $2 and $3, respectively. SRAM equ $20 ; value to remap SRAM to $2000-$20FF IOREG equ $03 ; value to remap I/O registers to $3000-$303F remap equ SRAM+IOREG INIT equ $1030 ldab #remap staa INIT …

6. External Memory Expansion Issues • address space assignment • address decoding • timing consideration Address space assignment - only unallocated memory space should be assigned to external memory components - memory space is often allocated in the unit of 2n KB (n is an integer) for 8-bit microcontrollers - address decoder can be simplified if memory space is divided into blocks of the same size. Allocated space for the 68HC11A8 $0000-$00FF: SRAM $1000-$103F: I/O registers $B600-B7FF: EEPROM $E000-$FFFF: ROM

7. Example 5.3 Assign the 68HC11 memory space using a block size of 4KB. Solution: The 64KB memory space can be divided into 16 4KB blocks.

8. Example 5.4 Assign the 68HC11 memory space using a block size of 8KB. Solution: The 64 KB space can be divided into eight 8KB blocks. Block number Address range $0000-$1FFF $2000-$3FFF $4000-$5FFF $6000-$7FFF $8000-$9FFF $A000-$BFFF $C000-$DFFF $E000-$FFFF 0 1 2 3 4 5 6 7 Address decoding methods - partial-decoding: each addressable location responds to more than one address on the system bus - full-decoding: each addressable location responds only to one specific address on the system bus

9. TTL Decoder Chips - 74138: a 3-to-8 decoder - 74139: dual 2-to-4 decoder

10. Example 5.5 Use a full decoding scheme to design an address decoder for a computer that has the following address space assignments: SRAM1: $2000-$3FFF ROM1: $4000-$5FFF E2PROM: $6000-$7FFF SRAM2: $A000-$BFFF ROM2: $C000-$DFFF Solution: Each memory component is 8KB. A 3-to-8 decoder 74LS138 can be used as the address decoder. The highest 3 address bits will be used as the address inputs to the decoder. The highest three address bits for each component are: SRAM1: 001 ROM1: 010 E2PROM: 011 SRAM2: 101 ROM2: 110 The decoder circuit is:

11. Example 5.6 Design an address decoder for a 68HC11-based product that has 2KB of external E2PROM and 2KB of external SRAM using partial decoding method. Solution: - Use the dual 2-to-4 decoder 74139 as the address decoder. - Divide the 64KB address space of the 68HC11 into four 16 KB blocks. - Use the two highest address signals A15A14 as the address inputs to the decoder. - Assign the address space $4000-$7FFF to E2PROM. - Assign the address space $8000-$BFFF to SRAM.

12. Example 5.7 Make space assignment for an 8-bit microcontroller-based system with 2 external 8KB SRAM chips, 2 8KB EPROM chips, 1 8KB flash memory chip, and 8 I/O devices. After making space assignment, design a decoder for it. Solution: Use a two-level space assignment and two 74138 to perform addressing decoding. The level one and level two space assignments are:

13. The decoding circuitry is as follows:

14. Conventions of Timing Diagrams - Ideal signals have 0 rise and fall times - A real signal has nonzero rise and fall times

15. - Normal signal representation - Unknown signals (when they are changing) representation

16. Floating signal representation - A floating signal is represented by a level half way between logic high and low.

17. Signal causal relationships

18. The 68HC11 Bus Cycle Timing Diagrams - A 68HC11 external bus cycle can only be performed in expanded mode and controlled by the E clock signal. - All read and write bus cycles take one E clock cycles to complete. - All timing parameters use 20% and 70% of the power supply voltage as reference points. (Motorola is using this convention) - Most timing parameters are measured relative to the rising and falling edges of the E clock signal. - The phrase before the rising edge of the E clock uses the time when the magnitude of the E clock signal is 0.2VDD as a reference point. - The phrase after the rising edge of the E clock uses the time when the magnitude of the E clock signal is 0.7VDD as a reference point. - The phrase before the falling edge of the E clock uses the time when the magnitude of the E clock signal is 0.7VDD as a reference point. - The phrase after the falling edge of the E clock uses the time when the magnitude of the E clock signal is 0.2VDD as a reference point.

19. MC68HC11 Read Bus Cycle Timing Diagram

20. For the 2 MHz E clock signal and the 68HC11 read bus cycle timing diagram - PWEL is the E clock low pulse width (227 ns) - PWEH is the E clock high pulse width (222 ns) - A15-A8 and R/W signals are valid tAV (94ns) before the rising edge of E clock - A15-A8 and R/W signal remain valid for tAH (30 ns) after the falling edge of E clock - A7-A0 and D7-D0 are multiplexed on the same PC7-PC0 pins - PC7-PC0 are used as A7-A0 when E clock is low - PC7-PC0 are used as D7-D0 when E clock is high - A7-A0 are valid tAVM (86 ns) before the rising edge of E clock - Read data must be valid for tDSR (30 ns) before the falling edge of E clock so that 68HC11 can read it correctly - Read data must remain valid for tDHR (0-83ns) after the falling edge of E clock so that 68HC11 can read it correctly - The falling edge of the AS signal is often used by the address latch to latch A7-A0 and A7-A0 remain valid for tAHL (26 ns) after AS falls - Multiplexed address delay is tMAD (83 ns) after the falling edge of E clock.

21. 68HC11 Write Bus Cycle Timing Diagram

22. For the 2 MHz E clock and the 68HC11 Write bus cycle timing diagram, most signals are identical to those in read bus cycle timing diagram except - the 68HC11 drives the data bus when E clock is high - the 68HC11 drives D7-D0 tDDW (128 ns) after the rising edge of the E clock until tDHW (33 ns) after the falling edge of the E clock

23. Adding an 8KB SRAM HM6264A to the 68HC11 - The HM6264A has 13 address pins to address each of the 8192 locations on the chip. - The HM6264A uses × 8 organization. - There are two chip enable signals: one (CS1) is active low, the other (CS2) is active high. - The active low signals WE and OE control the data in and out from the chip.

24. The HM6264A Read Cycle Timing Diagrams There are four access times: 1. Address access time (tAA) 2. CS1 access time (tCO1) 3. CS2 access time (tCO2) 4. OE access time (tOE)

25. HM6264A Write Cycle Timing diagram - Write data must be valid for tDW before WE goes high and remain valid for at least tDH after WE goes high - the pulse width of WE must be at least tWP

26. Interfacing the HM6264A-12 with the 2 MHz 68HC11 - Address space assigned to the HM6264A-12 is $4000-$5FFF - The 74F138, having a propagation delay of 8 ns, is used as the address decoder - The 74F373, having a propagation delay of 11.5 ns, is used as the low address latch - The WE signal is generated by NANDing the E clock and the inverting copy of R/W. - The NAND gate has a propagation delay of 15 ns. - The inverter that is used to invert the R/W signal has a propagation delay of 15 ns - The circuit connection is in Figure 5.17 of the next slide

28. Read Access Timing Analysis - Timing verification is illustrated using an overlapped 68HC11 and HM6264A timing diagram in Figure 5.18. - The time when the data outputs from the HM6264A become valid is determined by the last asserted input signal -- CS1 in this example - A15-A8 are valid 94 ns before E rises - A7-A0 are latched into the 74F373 at 41.5 ns before the rising edge of E clock The lower address signals A7-A0 are latched by the AS signal The AS signal falls to 0.7 VDD at 53 ns before the rising edge of E clock The 74F373 has a propagation of 11.5 ns A7-A0 is valid at 41.5 ns (53 - 11.5) before E rises - WE is high for a read cycle - E3 is the last asserted input signal for 74F138 and hence dictates the output valid time - O2 is asserted 8 ns after the rising edge of E clock - Data output from the HM6264A is valid 128 ns after the rising edge of the E clock or 94 ns (222 - 128) before the rising edge of the E clock -- this satisfies the 68HC11 read data setup time (30 ns)

30. - The data hold time is the smaller one (8ns - 43ns) of the following two values: 1. The output hold time from address change (tOH = 10 ns). Address inputs become invalid 33 ns after the E clock falls. Therefore, it holds up to 43 ns after E falls. 2. Chip selection CS1 to output in high impedance time tHZ1: 8 - 48 ns. - The data hold time requirement (0 to 83 ns) is violated. However, the data is held valid by the capacitance of the printed circuit board until other component drives the multiplexed address/data bus -- the earliest time is 138 ns after the falling edge of the E clock (or 53 ns before the rising edge of the next E clock cycle). - Both the read data setup and hold times are satisfied for the 68HC11. - The analysis about the PCB capacitance holds data valid follows:

31. Analysis on the duration of the data holding time by PCB capacitance - Each data pin (D7-D0) and the PCB ground plane form a capacitor - After memory chip stops driving data pins, the charge across the capacitor leaks away via 1. input leakage current into the 68HC11 data pin (on the order of 10 mA) 2. input leakage current into the memory chip (on the order of 2 mA) 3. other leakage paths on the printed circuit board - Let DV = voltage change required for a data bus signal to change from 1 to 0 and is 2.5V for a 5V power supply Dt = the time that it takes the voltage across the capacitor to drop by DV I = total leakage current C = the capacitance on the PCB. C is 20 pF/ft for a typical PCB Assume the data bus signal path is 1 foot long Then Dt = CDV ÷ I = 20 pF × 2.5 V ÷ 12 mA = 4 ms Even if the leakage current is ten times larger, the PCB capacitance can still hold the data for up to 400 ns.

32. Write Bus Cycle Timing Analysis - Timing verification is illustrated using an overlapped 68HC11 and HM6264A timing diagram in Figure 5.19. - The following timing parameters must be satisfied: 1. write cycle time (120 ns min.) 2. write pulse width (70 ns min.) 3. address setup time (0 ns min.) 4. address valid to end of write (85 ns min.) 5. data valid to end of write (50 ns min.) 6. data hold time (0 ns min.) 7. write recovery time (0 ns min.)

34. Calculation of Write Cycle Time Write cycle time is the period during which the address inputs to the HM6264A are valid and is equal to the sum of the following parameters: - Address inputs (A12-A0) to the HM6264A valid time before the rising edge of the E clock (A7-A0 become valid later than A12-A8). - E clock rise time (20 ns at 2 MHz) - Pulse width when the E clock is high - E clock fall time - Address inputs hold time after the E clock falls (33 ns). (A12-A8 become invalid earlier than A7-A0). tWC = 41.5 ns + tr + PWEH + tf + tAH = 336.5 ns (120 ns min. required)

35. Calculation of Write Pulse Width (WE) Since the WE signal is the NAND function of the R/W and E clock, the width is equal to the high pulse width of the E clock and is equal to 222 ns (70 ns is required).

36. Calculation of Address Setup Time The address setup time is measured from the moment that all address inputs are valid until the write enable signal goes low. A12-A8 become valid 94 ns before the rising edge of E clock and A7-A0 become valid 41.5 ns before the rising edge of the E clock. The WE signal becomes valid 15 ns after the rising edge of the E clock due to the propagation delay of the NAND gate. The address setup time is calculated as follows: tAS = 41.5 ns + tr + 15 ns = 76.5 ns The calculated value satisfies the requirement (0 ns min.).

37. Time from Address Valid till the End of Write This parameter is measured from the moment when all address inputs are valid until the write enable signal becomes invalid. This parameter is the sum of the following terms: 1. the lead time from address signals become valid to the rising edge of the E clock (41.5 ns) 2. the E clock rise time (20 ns) 3. the E clock high pulse width (222 ns) 4. the E clock fall time (20 ns) 5. the propagation delay of the NAND gate (15 ns) tAW = 41.5 ns + 20 ns + 222 ns + 20 ns + 15 ns = 318.5 ns (85 ns min. required)

38. Calculation of Write Data Setup Times The write data setup time (tDW) is measured from the moment that the 68HC11 drives the data on the data bus until the WE signal goes high (50 ns min. required). tDW = PWEH - t DDW + delay of the NAND gate = 222 ns - 128 ns + 15 ns = 109 ns 222 ns E tDDW D7-D0 15 ns write data setup time WE

39. Write Data Hold Time (tDH)Calculation - tDH is measured from the moment when WE becomes invalid until D7-D0 become invalid. tDH = tDHW - NAND delay = 33 ns - 15 ns = 18 ns (> 0 ns) E 15 ns WE tDH tDHW = 33 ns D7-D0

40. Calculation of Write Recovery Time Write recovery time (tWR) is measured from the moment that the earliest chip select signal (CS1 in this example) becomes invalid until the moment that the address signals are invalid. The calculation of tWR is illustrated in Figure 5.23. All timing parameters have been verified to satisfy the requirements.