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ECE 545 Introduction to VHDL Course web page: ECE web page Courses Course web pages ECE 545 http://ece.gmu.edu/courses/ECE545/index.htm
Kris Gaj • Research and teaching interests: • reconfigurable computing • computer arithmetic • cryptography • network security • Contact: • Science & Technology II, room 223 • kgaj01@yahoo.com, kgaj@gmu.edu • (703) 993-1575 Office hours:Wednesday, Thursday 7:30-8:30 PM and by appointment
ECE 545 Part of: MS in Computer Engineering Required course in two concentration areas: Digital Systems Design Microprocessor and Embedded Systems Elective course in the remaining concentration areas MS in Electrical Engineering Elective
DIGITAL SYSTEMS DESIGN • Concentration advisor: Ken Hintz • ECE 545 Introduction to VHDL – K. Gaj, D. Hwang, K. Hintz, project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • ECE 645 Computer Arithmetic: HW and SWImplementation – K. Gaj, project, VHDL/Verilog, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • ECE 586 Digital Integrated Circuits – D. Ioannou • ECE 681 VLSI Design Automation – T. Storey, project/lab, back-end design with Synopsys tools
MICROPROCESSOR AND EMBEDDED SYSTEMS • Concentration advisor: Ron Barnes • ECE 511 Microprocessors– R. Barnes, P. Pachowicz, • ECE 545 Introduction to VHDL– K. Gaj, D. Hwang, K. Hintz,project, VHDL, Aldec/Synplicity/Xilinx and ModelSim/Synopsys • ECE 611 Advanced Microprocessors– R. Barnes • ECE 612 Real-Time Embedded Systems– H. Camp, K. Hintz, D. Hwang
Concentration Area Advisors DIGITAL SYSTEMS DESIGN: Ken Hintz COMPUTER NETWORKS: Brian Mark NETWORK AND SYSTEM SECURITY:Kris Gaj MICROPROCESSOR AND EMBEDDED SYSTEMS: Ron Barnes
Core courses • There are TWO core courses common for all concentration • areas: • CS 571 Operating Systems – H. Aydin, S. Setia, C. Snow, project, C/C++ or Java • Pros: • Prerequisite for many other courses and projects • HLL (High Level Language) refresher • Offered regularly in Fall and Spring • ECE 548 Sequential Machine Theory – K. Hintz, R. Schneider • Pros: • Common theoretical and mathematical foundation used in all • concentrations • Offered regularly in Spring • Not a strong prerequisite for any other course; can be taken any time • during the curriculum.
CpE EE Microprocessors and Embedded Systems Control and Robotics CS 571 Operating Systems ECE 548 Sequential Machine Theory Core Courses ECE 521 Modern Systems Theory and ECE 528 or 548 or 584 ECE 511 Microprocessors ECE 545 Introduction to VHDL ECE 611 Advanced Microprocessors ECE 612 Real Time Embedded Systems 3 out of 4: ECE 612 Real Time Embedded Systems ECE 620 Optimal Control Theory ECE 624 Control Systems ECE 673 Discrete Event Systems Required Courses ECE electives including ECE 670, 671 (C4I) ECE 542, 642 (communications) ECE 535, 635 (signal processing) CpE Electives including CS 540, 583 (languages, algorithms) CS 635 (parallel machines) ECE 542, 642, 742 (networks) ECE 645, 681 (digital design) Electives J. Gertler, G. Cook, K. Hintz,A. Levis R. Barnes, P. Pachowicz, K. Hintz, D. Hwang, K. Gaj Professors
ECE 545 Projects Lecture Project 1 30 % Project 2p15 % Project 2s 5 % Homework 10 % Midterm exams Midterm 1 20 % in class Midterm 2 20 % take home
Lecture (1) Lecture 1 - Introduction to VHDL for Synthesis Lecture 2 - Data Flow and Structural Modeling of Combinational Logic. Packages and Components. Hands-on Session 1: VHDL Simulators: Active HDL and ModelSim Lecture 3 – Behavioral Modeling of Sequential Logic. Registers, Counters, Shift Registers.Simple Testbenches. Lecture 4 - Introduction to FPGA Devices & Tools Hands-on Session 2: Tools for FPGA Synthesis and Implemenation Lecture 5 - Finite State Machines Lecture 6 - Algorithmic State Machines. Memories: RAM, ROM. Lecture 7 – Advanced Testbenches. File I/O. Lecture 8 - Mixed Style RTL Modeling Advanced Examples: Sorting, Average, MAX, MIN Midterm 1
Lecture (2) Lecture 9 – ASIC Logic Synthesis with Synopsys Design Compiler Hands-on Session 3: ASIC Synthesis - Synopsys Design Compiler Lecture 10 – Timing of Digital Systems Hands-on Session 4: ASIC Timing Analysis - Synopsys PrimeTime Lecture 11 - Variables, Functions and Procedures Lecture 12 – Advanced Data Types. Operators and Attributes. Lecture 13 - Behavioral Modeling - The DLX Computer System Lecture 14 – Discrete Event Simulators. VHDL vs. Verilog. Midterm Exam 2
Textbooks Required Textbooks: Volnei A. Pedroni, Circuit Design with VHDL, The MIT Press, 2004 Sundar Rajan, Essential VHDL: RTL Synthesis Done Right, S & G Publishing, 1998 Supplementary Textbooks: Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, 2nd Edition, McGraw-Hill, 2005 Peter J. Ashenden, The Designer's Guide to VHDL, 2nd Edition, San Francisco:Morgan Kaufman, 1996, 2002
Midterm exam 1 • 2 hours 30 minutes • in class • design-oriented • open-books, open-notes • practice exams will be available on the web Tentative date: Thursday, October 26th
Midterm Exam 2 • take-home • full design, including logic synthesis and timing analysis for FPGAs or ASICs • 48 hours Tentative date: Saturday, Sunday, December 9-10
Project technologies FPGA: Field Programmable Gate Arrays and ASIC: semi-custom Application Specific Integrated Circuits
World of Integrated Circuits Integrated Circuits Full-Custom ASICs Semi-Custom ASICs User Programmable PLD FPGA PAL PLA PML LUT (Look-Up Table) MUX Gates
Two competing implementation approaches FPGA FieldProgrammable GateArray ASIC ApplicationSpecific IntegratedCircuit • bought off the shelf • and reconfigured by • designers themselves • designs must be sent • for expensive and time • consuming fabrication • in semiconductor foundry • no physical layout design; • design ends with • a bitstream used • to configure a device • designed all the way • from behavioral description • to physical layout
Which Way to Go? ASICs FPGAs Off-the-shelf High performance Low development cost Low power Short time to market Low cost in high volumes Reconfigurability
I/O Block I/O Block I/O Block I/O Block What is an FPGA Chip ? • Field Programmable Gate Array • A chip that can be configured by user to implement different digital hardware • Configurable Logic Blocks and Programmable Switch Matrices • Bitstream to configure: function of each block & the interconnection between logic blocks Source: [Brown99]
CLB Slice COUT YB Carry & Control Logic Look-Up Table Y G4 G3 G2 G1 S D Q O CK EC R F5IN BY SR XB Look-Up Table Carry & Control Logic X S F4 F3 F2 F1 D Q O CK EC R CIN CLK CE SLICE
LUT (Look-Up Table) Functionality • Look-Up tables are primary elements for logic implementation • Each LUT can implement any function of 4 inputs
Major FPGA Vendors SRAM-based FPGAs • Xilinx, Inc. • Altera Corp. • Atmel • Lattice Semiconductor Flash & antifuse FPGAs • Actel Corp. • Quick Logic Corp. Share over 60% of the market
Xilinx FPGA Families • Old families • XC3000, XC4000, XC5200 old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs. • Low-cost families • Spartan/XL – derived from XC4000 • Spartan-II – derived from Virtex • Spartan-IIE – derived from Virtex-E • Spartan-3 • High-performance families • Virtex (0.22µm) • Virtex-E, Virtex-EM (0.18µm) • Virtex-II, Virtex-II PRO (0.13µm) • Virtex-4 (0.09µm)
Design process (1) Specification Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. VHDL description (Your VHDL Source Files) Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31downto0); data_output: out std_logic_vector(31downto0); out_full: in std_logic; key_input: in std_logic_vector(31downto0); key_read: out std_logic; ); end AES_core; Functional simulation Synthesis Post-synthesis simulation
Design process (2) Implementation (Mapping, Placing & Routing) Timing simulation Configuration On chip testing
Logic Synthesis VHDL description Circuit netlist architecture MLU_DATAFLOW of MLU is signal A1:STD_LOGIC; signal B1:STD_LOGIC; signal Y1:STD_LOGIC; signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC; begin A1<=A when (NEG_A='0') else not A; B1<=B when (NEG_B='0') else not B; Y<=Y1 when (NEG_Y='0') else not Y1; MUX_0<=A1 and B1; MUX_1<=A1 or B1; MUX_2<=A1 xor B1; MUX_3<=A1 xnor B1; with (L1 & L0) select Y1<=MUX_0 when "00", MUX_1 when "01", MUX_2 when "10", MUX_3 when others; end MLU_DATAFLOW;
Features of synthesis tools • Interpret RTL code • Produce synthesized circuit netlist in a standard EDIF format • Give preliminary performance estimates • Some can display circuit schematics corresponding to EDIF netlist
Implementation • After synthesis the entireimplementation process is performed by FPGA vendor tools
